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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz6e4b0832019-01-31 10:48:47 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +00007#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +00008#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <common/bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
11
12 .globl bl2_entrypoint
13
14
Achin Gupta4f6ad662013-10-25 09:08:21 +010015
Andrew Thoelke38bde412014-03-18 13:46:55 +000016func bl2_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010017 /*---------------------------------------------
Soby Mathew73308d02018-01-09 14:36:14 +000018 * Save arguments x0 - x3 from BL1 for future
19 * use.
Achin Gupta4f6ad662013-10-25 09:08:21 +010020 * ---------------------------------------------
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +000021 */
Soby Mathew73308d02018-01-09 14:36:14 +000022 mov x20, x0
23 mov x21, x1
24 mov x22, x2
25 mov x23, x3
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27 /* ---------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000028 * Set the exception vector to something sane.
29 * ---------------------------------------------
30 */
31 adr x0, early_exceptions
32 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +010033 isb
34
35 /* ---------------------------------------------
36 * Enable the SError interrupt now that the
37 * exception vectors have been setup.
38 * ---------------------------------------------
39 */
40 msr daifclr, #DAIF_ABT_BIT
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000041
42 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +010043 * Enable the instruction cache, stack pointer
John Tsichritzisd5a59602019-03-04 16:42:54 +000044 * and data access alignment checks and disable
45 * speculative loads.
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000046 * ---------------------------------------------
47 */
Achin Gupta9f098352014-07-18 18:38:28 +010048 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000049 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +010050 orr x0, x0, x1
John Tsichritzisd5a59602019-03-04 16:42:54 +000051 bic x0, x0, #SCTLR_DSSBS_BIT
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000052 msr sctlr_el1, x0
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000053 isb
54
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000055 /* ---------------------------------------------
Achin Guptae9c4a642015-09-11 16:03:13 +010056 * Invalidate the RW memory used by the BL2
57 * image. This includes the data and NOBITS
58 * sections. This is done to safeguard against
59 * possible corruption of this memory by dirty
60 * cache lines in a system cache as a result of
61 * use by an earlier boot loader stage.
62 * ---------------------------------------------
63 */
64 adr x0, __RW_START__
65 adr x1, __RW_END__
66 sub x1, x1, x0
67 bl inv_dcache_range
68
69 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000070 * Zero out NOBITS sections. There are 2 of them:
71 * - the .bss section;
72 * - the coherent memory section.
73 * ---------------------------------------------
74 */
Soby Mathewfcaf1bd2018-10-12 16:40:28 +010075 adrp x0, __BSS_START__
76 add x0, x0, :lo12:__BSS_START__
77 adrp x1, __BSS_END__
78 add x1, x1, :lo12:__BSS_END__
79 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +000080 bl zeromem
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000081
Soby Mathew2ae20432015-01-08 18:02:44 +000082#if USE_COHERENT_MEM
Soby Mathewfcaf1bd2018-10-12 16:40:28 +010083 adrp x0, __COHERENT_RAM_START__
84 add x0, x0, :lo12:__COHERENT_RAM_START__
85 adrp x1, __COHERENT_RAM_END_UNALIGNED__
86 add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
87 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +000088 bl zeromem
Soby Mathew2ae20432015-01-08 18:02:44 +000089#endif
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000090
Achin Gupta4f6ad662013-10-25 09:08:21 +010091 /* --------------------------------------------
Achin Guptaf4a97092014-06-25 19:26:22 +010092 * Allocate a stack whose memory will be marked
93 * as Normal-IS-WBWA when the MMU is enabled.
94 * There is no risk of reading stale stack
95 * memory after enabling the MMU as only the
96 * primary cpu is running at the moment.
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 * --------------------------------------------
98 */
Soby Mathew3700a922015-07-13 11:21:11 +010099 bl plat_set_my_stack
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100
101 /* ---------------------------------------------
Douglas Raillard306593d2017-02-24 18:14:15 +0000102 * Initialize the stack protector canary before
103 * any C code is called.
104 * ---------------------------------------------
105 */
106#if STACK_PROTECTOR_ENABLED
107 bl update_stack_protector_canary
108#endif
109
110 /* ---------------------------------------------
Antonio Nino Diaz6e4b0832019-01-31 10:48:47 +0000111 * Perform BL2 setup
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112 * ---------------------------------------------
113 */
Yatharth Kochar57d334c2015-10-29 12:47:02 +0000114 mov x0, x20
Soby Mathew73308d02018-01-09 14:36:14 +0000115 mov x1, x21
116 mov x2, x22
117 mov x3, x23
Antonio Nino Diaz6e4b0832019-01-31 10:48:47 +0000118 bl bl2_setup
Soby Mathew73308d02018-01-09 14:36:14 +0000119
Antonio Nino Diaz6e4b0832019-01-31 10:48:47 +0000120 /* ---------------------------------------------
121 * Enable pointer authentication
122 * ---------------------------------------------
123 */
124#if ENABLE_PAUTH
125 mrs x0, sctlr_el1
126 orr x0, x0, #SCTLR_EnIA_BIT
127 msr sctlr_el1, x0
128 isb
129#endif /* ENABLE_PAUTH */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130
131 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132 * Jump to main function.
133 * ---------------------------------------------
134 */
135 bl bl2_main
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000136
137 /* ---------------------------------------------
138 * Should never reach this point.
139 * ---------------------------------------------
140 */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000141 no_ret plat_panic_handler
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000142
Kévin Petita877c252015-03-24 14:03:57 +0000143endfunc bl2_entrypoint