blob: 2f058da9fc9e2f586d315e39ed1d98eb575b0b2b [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35
36 .globl bl2_entrypoint
37
38
Achin Gupta4f6ad662013-10-25 09:08:21 +010039
Andrew Thoelke38bde412014-03-18 13:46:55 +000040func bl2_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010041 /*---------------------------------------------
42 * Store the extents of the tzram available to
43 * BL2 for future use. Use the opcode param to
44 * allow implement other functions if needed.
45 * ---------------------------------------------
46 */
47 mov x20, x0
48 mov x21, x1
Achin Gupta4f6ad662013-10-25 09:08:21 +010049
50 /* ---------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000051 * Set the exception vector to something sane.
52 * ---------------------------------------------
53 */
54 adr x0, early_exceptions
55 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +010056 isb
57
58 /* ---------------------------------------------
59 * Enable the SError interrupt now that the
60 * exception vectors have been setup.
61 * ---------------------------------------------
62 */
63 msr daifclr, #DAIF_ABT_BIT
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000064
65 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +010066 * Enable the instruction cache, stack pointer
67 * and data access alignment checks
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000068 * ---------------------------------------------
69 */
Achin Gupta9f098352014-07-18 18:38:28 +010070 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000071 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +010072 orr x0, x0, x1
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000073 msr sctlr_el1, x0
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000074 isb
75
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000076 /* ---------------------------------------------
Sandrine Bailleux34edaed2013-12-02 15:45:07 +000077 * Check the opcodes out of paranoia.
78 * ---------------------------------------------
79 */
80 mov x0, #RUN_IMAGE
81 cmp x0, x20
82 b.ne _panic
83
84 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000085 * Zero out NOBITS sections. There are 2 of them:
86 * - the .bss section;
87 * - the coherent memory section.
88 * ---------------------------------------------
89 */
90 ldr x0, =__BSS_START__
91 ldr x1, =__BSS_SIZE__
92 bl zeromem16
93
94 ldr x0, =__COHERENT_RAM_START__
95 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
96 bl zeromem16
97
Achin Gupta4f6ad662013-10-25 09:08:21 +010098 /* --------------------------------------------
Achin Guptaf4a97092014-06-25 19:26:22 +010099 * Allocate a stack whose memory will be marked
100 * as Normal-IS-WBWA when the MMU is enabled.
101 * There is no risk of reading stale stack
102 * memory after enabling the MMU as only the
103 * primary cpu is running at the moment.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 * --------------------------------------------
105 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100106 mrs x0, mpidr_el1
Achin Guptaf4a97092014-06-25 19:26:22 +0100107 bl platform_set_stack
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108
109 /* ---------------------------------------------
110 * Perform early platform setup & platform
111 * specific early arch. setup e.g. mmu setup
112 * ---------------------------------------------
113 */
114 mov x0, x21
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 bl bl2_early_platform_setup
116 bl bl2_plat_arch_setup
117
118 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119 * Jump to main function.
120 * ---------------------------------------------
121 */
122 bl bl2_main
123_panic:
124 b _panic