Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef DDR_INIT_E3_H |
| 8 | #define DDR_INIT_E3_H |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 9 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 10 | #include <stdint.h> |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 11 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 12 | #define RCAR_E3_DDR_VERSION "rev.0.11" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 13 | |
| 14 | #ifdef ddr_qos_init_setting |
| 15 | #define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */ |
| 16 | #else |
| 17 | #if RCAR_REF_INT == 0 |
| 18 | #define REFRESH_RATE 3900 |
| 19 | #elif RCAR_REF_INT == 1 |
| 20 | #define REFRESH_RATE 7800 |
| 21 | #else |
| 22 | #define REFRESH_RATE 3900 |
| 23 | #endif |
| 24 | #endif |
| 25 | |
ldts | 0a596b4 | 2018-11-06 10:17:12 +0100 | [diff] [blame] | 26 | extern int32_t rcar_dram_init(void); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 27 | #define INITDRAM_OK (0) |
| 28 | #define INITDRAM_NG (0xffffffff) |
| 29 | #define INITDRAM_ERR_I (0xffffffff) |
| 30 | #define INITDRAM_ERR_O (0xfffffffe) |
| 31 | #define INITDRAM_ERR_T (0xfffffff0) |
| 32 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 33 | #endif /* DDR_INIT_E3_H */ |