Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / d52f24884e10d96dd6efc133473c6ba489f034e9 / . / plat / intel / soc / stratix10 / platform.mk
blob: 4cd7032e1e574e8e1921ba48eea9663015b6a216 [file] [log] [blame]
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]1#
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600[diff] [blame]2# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
Sieu Mun Tang9dd2c182024-10-22 01:00:45 +0800[diff] [blame]3# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
4# Copyright (c) 2024, Altera Corporation. All rights reserved.
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]5#
6# SPDX-License-Identifier: BSD-3-Clause
7#
8
9PLAT_INCLUDES := \
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]10 -Iplat/intel/soc/stratix10/include/ \
Hadi Asyrafi309ac012019-08-01 14:48:39 +0800[diff] [blame]11 -Iplat/intel/soc/common/drivers/ \
12 -Iplat/intel/soc/common/include/
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]13
Abdul Halim, Muhammad Hadi Asyrafi0ae8d9a2020-08-19 14:50:01 +0800[diff] [blame]14# Include GICv2 driver files
15include drivers/arm/gic/v2/gicv2.mk
16AGX_GICv2_SOURCES := \
17 ${GICV2_SOURCES} \
18 plat/common/plat_gicv2.c
19
20
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]21PLAT_BL_COMMON_SOURCES := \
Abdul Halim, Muhammad Hadi Asyrafi0ae8d9a2020-08-19 14:50:01 +0800[diff] [blame]22 ${AGX_GICv2_SOURCES} \
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]23 drivers/delay_timer/delay_timer.c \
24 drivers/delay_timer/generic_delay_timer.c \
25 drivers/ti/uart/aarch64/16550_console.S \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]26 lib/xlat_tables/aarch64/xlat_tables.c \
27 lib/xlat_tables/xlat_tables_common.c \
Hadi Asyrafi309ac012019-08-01 14:48:39 +0800[diff] [blame]28 plat/intel/soc/common/aarch64/platform_common.c \
Chee Hong Ang64740962020-05-11 00:55:01 +0800[diff] [blame]29 plat/intel/soc/common/aarch64/plat_helpers.S \
Sieu Mun Tang9dd2c182024-10-22 01:00:45 +0800[diff] [blame]30 plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
Abdul Halim, Muhammad Hadi Asyrafi2f94ca42020-08-05 22:40:46 +0800[diff] [blame]31 plat/intel/soc/common/socfpga_delay_timer.c \
32 plat/intel/soc/common/soc/socfpga_firewall.c
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]33
34BL2_SOURCES += \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]35 common/desc_image_load.c \
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]36 drivers/mmc/mmc.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]37 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]38 drivers/io/io_storage.c \
39 drivers/io/io_block.c \
40 drivers/io/io_fip.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]41 drivers/partition/partition.c \
42 drivers/partition/gpt.c \
43 drivers/synopsys/emmc/dw_mmc.c \
44 lib/cpus/aarch64/cortex_a53.S \
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]45 plat/intel/soc/stratix10/bl2_plat_setup.c \
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]46 plat/intel/soc/stratix10/soc/s10_clock_manager.c \
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]47 plat/intel/soc/stratix10/soc/s10_memory_controller.c \
Sieu Mun Tange026eea2022-05-05 23:42:55 +0800[diff] [blame]48 plat/intel/soc/stratix10/soc/s10_mmc.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]49 plat/intel/soc/stratix10/soc/s10_pinmux.c \
BenjaminLimJLa4a43272022-04-06 10:19:16 +0800[diff] [blame]50 plat/intel/soc/common/bl2_plat_mem_params_desc.c \
Hadi Asyrafi6a240c72019-08-01 15:21:20 +0800[diff] [blame]51 plat/intel/soc/common/socfpga_image_load.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]52 plat/intel/soc/common/socfpga_storage.c \
Tien Hock, Loh8d9e8912019-10-02 13:49:25 +0800[diff] [blame]53 plat/intel/soc/common/soc/socfpga_emac.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]54 plat/intel/soc/common/soc/socfpga_handoff.c \
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +0800[diff] [blame]55 plat/intel/soc/common/soc/socfpga_mailbox.c \
Hadi Asyrafi67cb0ea2019-12-23 13:25:33 +0800[diff] [blame]56 plat/intel/soc/common/soc/socfpga_reset_manager.c \
Hadi Asyrafic461add2019-06-12 11:24:12 +0800[diff] [blame]57 plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
Jit Loon Lim477aef42023-08-14 13:12:01 +0800[diff] [blame]58 plat/intel/soc/common/drivers/ddr/ddr.c \
Hadi Asyrafic461add2019-06-12 11:24:12 +0800[diff] [blame]59 plat/intel/soc/common/drivers/wdt/watchdog.c
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]60
Rohit Nerdce970c2022-05-11 03:18:31 -0700[diff] [blame]61include lib/zlib/zlib.mk
62PLAT_INCLUDES += -Ilib/zlib
63BL2_SOURCES += $(ZLIB_SOURCES)
64
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]65BL31_SOURCES += \
66 drivers/arm/cci/cci.c \
67 lib/cpus/aarch64/aem_generic.S \
Tien Hock, Lohab34f742019-02-26 09:25:14 +0800[diff] [blame]68 lib/cpus/aarch64/cortex_a53.S \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]69 plat/common/plat_psci_common.c \
BenjaminLimJLa4a43272022-04-06 10:19:16 +0800[diff] [blame]70 plat/intel/soc/stratix10/soc/s10_clock_manager.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]71 plat/intel/soc/stratix10/bl31_plat_setup.c \
72 plat/intel/soc/common/socfpga_psci.c \
73 plat/intel/soc/common/socfpga_sip_svc.c \
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800[diff] [blame]74 plat/intel/soc/common/socfpga_sip_svc_v2.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]75 plat/intel/soc/common/socfpga_topology.c \
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]76 plat/intel/soc/common/sip/socfpga_sip_ecc.c \
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800[diff] [blame]77 plat/intel/soc/common/sip/socfpga_sip_fcs.c \
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800[diff] [blame]78 plat/intel/soc/common/soc/socfpga_mailbox.c \
Hadi Asyrafi36a9f302019-12-24 10:42:52 +0800[diff] [blame]79 plat/intel/soc/common/soc/socfpga_reset_manager.c
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]80
Sieu Mun Tangd52f2482024-10-24 22:16:50 +0800[diff] [blame^]81# Don't have the Linux kernel as a BL33 image by default
82ARM_LINUX_KERNEL_AS_BL33 := 0
83$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
84$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
Jit Loon Limc5a3e3a2023-10-16 00:19:34 +0800[diff] [blame]85$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
86
Sieu Mun Tangd52f2482024-10-24 22:16:50 +0800[diff] [blame^]87# Configs for Boot Source
88SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
89SOCFPGA_BOOT_SOURCE_QSPI ?= 0
90SOCFPGA_BOOT_SOURCE_NAND ?= 0
91
92$(eval $(call assert_booleans,\
93 $(sort \
94 SOCFPGA_BOOT_SOURCE_SDMMC \
95 SOCFPGA_BOOT_SOURCE_QSPI \
96 SOCFPGA_BOOT_SOURCE_NAND \
97)))
98$(eval $(call add_defines,\
99 $(sort \
100 SOCFPGA_BOOT_SOURCE_SDMMC \
101 SOCFPGA_BOOT_SOURCE_QSPI \
102 SOCFPGA_BOOT_SOURCE_NAND \
103)))
104
Loh Tien Hock59400a42019-02-04 16:17:24 +0800[diff] [blame]105PROGRAMMABLE_RESET_ADDRESS := 0
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600[diff] [blame]106RESET_TO_BL2 := 1
Tien Hock, Lohab34f742019-02-26 09:25:14 +0800[diff] [blame]107USE_COHERENT_MEM := 1