| commit | 9dd2c1826b60aada7b1d28dc8fa678d207e9428e | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Tue Oct 22 01:00:45 2024 +0800 |
| committer | Sieu Mun Tang <sieu.mun.tang@intel.com> | Tue Oct 22 01:07:19 2024 +0800 |
| tree | 8c1dc8b43084b183eccd0366f07ca8021d709db8 | |
| parent | 76097304acb0ca52381278e8c0a6aab89a52cc0f [diff] |
fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset This fix is to flush and invalidate the caches before cold reset. Issue happen where Agilex5 hardware does not support the caches flush. Thus software workaround is needed. Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>