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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley0cdebbd2015-03-30 17:15:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_HELPERS_H__
32#define __ARCH_HELPERS_H__
33
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010034#include <arch.h> /* for additional register definitions */
35#include <cdefs.h> /* For __dead2 */
36#include <stdint.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010037
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010038/**********************************************************************
39 * Macros which create inline functions to read or write CPU system
40 * registers
41 *********************************************************************/
42
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000043#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
44static inline uint64_t read_ ## _name(void) \
45{ \
46 uint64_t v; \
47 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
48 return v; \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010049}
50
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000051#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
52static inline void write_ ## _name(uint64_t v) \
53{ \
54 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010055}
56
57#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000058static inline void write_ ## _name(const uint64_t v) \
59{ \
60 __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010061}
62
63/* Define read function for system register */
64#define DEFINE_SYSREG_READ_FUNC(_name) \
65 _DEFINE_SYSREG_READ_FUNC(_name, _name)
66
67/* Define read & write function for system register */
68#define DEFINE_SYSREG_RW_FUNCS(_name) \
69 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
70 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
71
72/* Define read & write function for renamed system register */
73#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
74 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
75 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
76
Achin Gupta92712a52015-09-03 14:18:02 +010077/* Define read function for renamed system register */
78#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
79 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
80
81/* Define write function for renamed system register */
82#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
83 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
84
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010085/* Define write function for special system registers */
86#define DEFINE_SYSREG_WRITE_CONST_FUNC(_name) \
87 _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _name)
88
89
90/**********************************************************************
91 * Macros to create inline functions for system instructions
92 *********************************************************************/
93
94/* Define function for simple system instruction */
95#define DEFINE_SYSOP_FUNC(_op) \
Juan Castillo2d552402014-06-13 17:05:10 +010096static inline void _op(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010097{ \
98 __asm__ (#_op); \
99}
100
101/* Define function for system instruction with type specifier */
102#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
Juan Castillo2d552402014-06-13 17:05:10 +0100103static inline void _op ## _type(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100104{ \
105 __asm__ (#_op " " #_type); \
106}
107
108/* Define function for system instruction with register parameter */
109#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
110static inline void _op ## _type(uint64_t v) \
111{ \
112 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
113}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114
115/*******************************************************************************
Achin Guptaa0cd9892014-02-09 13:30:38 +0000116 * Aarch64 translation tables manipulation helper prototypes
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100117******************************************************************************/
118uint64_t create_table_desc(uint64_t *next_table_ptr);
119uint64_t create_block_desc(uint64_t desc, uint64_t addr, uint32_t level);
120uint64_t create_device_block(uint64_t output_addr, uint32_t level, uint32_t ns);
121uint64_t create_romem_block(uint64_t output_addr, uint32_t level, uint32_t ns);
122uint64_t create_rwmem_block(uint64_t output_addr, uint32_t level, uint32_t ns);
Achin Guptaa0cd9892014-02-09 13:30:38 +0000123
124/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125 * TLB maintenance accessor prototypes
126 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100127DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
128DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
129DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
130DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
131DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
132DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
133DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134
135/*******************************************************************************
136 * Cache maintenance accessor prototypes
137 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100138DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
139DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
140DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
141DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
142DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
143DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
144DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
145DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
146
Varun Wadekar97625e32015-03-13 14:59:03 +0530147/*******************************************************************************
148 * Address translation accessor prototypes
149 ******************************************************************************/
150DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
151DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
152DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
153DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
154
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100155void flush_dcache_range(uint64_t, uint64_t);
Achin Guptae9c4a642015-09-11 16:03:13 +0100156void clean_dcache_range(uint64_t, uint64_t);
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100157void inv_dcache_range(uint64_t, uint64_t);
158void dcsw_op_louis(uint32_t);
159void dcsw_op_all(uint32_t);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160
Dan Handleya17fefa2014-05-14 12:38:32 +0100161void disable_mmu_el3(void);
162void disable_mmu_icache_el3(void);
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100163
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164/*******************************************************************************
165 * Misc. accessor prototypes
166 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100168DEFINE_SYSREG_WRITE_CONST_FUNC(daifset)
169DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100171#define enable_irq() write_daifclr(DAIF_IRQ_BIT)
172#define enable_fiq() write_daifclr(DAIF_FIQ_BIT)
173#define enable_serror() write_daifclr(DAIF_ABT_BIT)
174#define enable_debug_exceptions() write_daifclr(DAIF_DBG_BIT)
175#define disable_irq() write_daifset(DAIF_IRQ_BIT)
176#define disable_fiq() write_daifset(DAIF_FIQ_BIT)
177#define disable_serror() write_daifset(DAIF_ABT_BIT)
178#define disable_debug_exceptions() write_daifset(DAIF_DBG_BIT)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179
Varun Wadekar97625e32015-03-13 14:59:03 +0530180DEFINE_SYSREG_READ_FUNC(par_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100181DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
182DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
183DEFINE_SYSREG_READ_FUNC(CurrentEl)
184DEFINE_SYSREG_RW_FUNCS(daif)
185DEFINE_SYSREG_RW_FUNCS(spsr_el1)
186DEFINE_SYSREG_RW_FUNCS(spsr_el2)
187DEFINE_SYSREG_RW_FUNCS(spsr_el3)
188DEFINE_SYSREG_RW_FUNCS(elr_el1)
189DEFINE_SYSREG_RW_FUNCS(elr_el2)
190DEFINE_SYSREG_RW_FUNCS(elr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100192DEFINE_SYSOP_FUNC(wfi)
193DEFINE_SYSOP_FUNC(wfe)
194DEFINE_SYSOP_FUNC(sev)
195DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
Soby Mathewed995662014-12-30 16:11:42 +0000196DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
197DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
198DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100199DEFINE_SYSOP_FUNC(isb)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100201uint32_t get_afflvl_shift(uint32_t);
202uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100205void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
206 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
207void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
208 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209
210/*******************************************************************************
211 * System register accessor prototypes
212 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100213DEFINE_SYSREG_READ_FUNC(midr_el1)
214DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100216DEFINE_SYSREG_RW_FUNCS(scr_el3)
217DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100219DEFINE_SYSREG_RW_FUNCS(vbar_el1)
220DEFINE_SYSREG_RW_FUNCS(vbar_el2)
221DEFINE_SYSREG_RW_FUNCS(vbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100223DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
224DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
225DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100226
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100227DEFINE_SYSREG_RW_FUNCS(actlr_el1)
228DEFINE_SYSREG_RW_FUNCS(actlr_el2)
229DEFINE_SYSREG_RW_FUNCS(actlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100231DEFINE_SYSREG_RW_FUNCS(esr_el1)
232DEFINE_SYSREG_RW_FUNCS(esr_el2)
233DEFINE_SYSREG_RW_FUNCS(esr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100234
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100235DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
236DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
237DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100239DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
240DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
241DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100243DEFINE_SYSREG_RW_FUNCS(far_el1)
244DEFINE_SYSREG_RW_FUNCS(far_el2)
245DEFINE_SYSREG_RW_FUNCS(far_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100247DEFINE_SYSREG_RW_FUNCS(mair_el1)
248DEFINE_SYSREG_RW_FUNCS(mair_el2)
249DEFINE_SYSREG_RW_FUNCS(mair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100250
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100251DEFINE_SYSREG_RW_FUNCS(amair_el1)
252DEFINE_SYSREG_RW_FUNCS(amair_el2)
253DEFINE_SYSREG_RW_FUNCS(amair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100255DEFINE_SYSREG_READ_FUNC(rvbar_el1)
256DEFINE_SYSREG_READ_FUNC(rvbar_el2)
257DEFINE_SYSREG_READ_FUNC(rvbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100259DEFINE_SYSREG_RW_FUNCS(rmr_el1)
260DEFINE_SYSREG_RW_FUNCS(rmr_el2)
261DEFINE_SYSREG_RW_FUNCS(rmr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100263DEFINE_SYSREG_RW_FUNCS(tcr_el1)
264DEFINE_SYSREG_RW_FUNCS(tcr_el2)
265DEFINE_SYSREG_RW_FUNCS(tcr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100267DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
268DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
269DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100271DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000273DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
274
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100275DEFINE_SYSREG_RW_FUNCS(cptr_el2)
276DEFINE_SYSREG_RW_FUNCS(cptr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100278DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
279DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
280DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
281DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
282DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
283DEFINE_SYSREG_READ_FUNC(cntpct_el0)
284DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100285
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100286DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100287
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100288DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
289
Andrew Thoelke4e126072014-06-04 21:10:52 +0100290DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
291DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
292
Soby Mathew26fb90e2015-01-06 21:36:55 +0000293DEFINE_SYSREG_READ_FUNC(isr_el1)
294
Dan Handley0cdebbd2015-03-30 17:15:16 +0100295DEFINE_SYSREG_READ_FUNC(ctr_el0)
296
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100297DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
298DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
299DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
300DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100301DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
302DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
303DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
304DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
305DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
306DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
307DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
308DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100311#define IS_IN_EL(x) \
312 (GET_EL(read_CurrentEl()) == MODE_EL##x)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100313
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100314#define IS_IN_EL1() IS_IN_EL(1)
315#define IS_IN_EL3() IS_IN_EL(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100316
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100317/* Previously defined accesor functions with incomplete register names */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100318
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100319#define read_current_el() read_CurrentEl()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100321#define dsb() dsbsy()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100322
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100323#define read_midr() read_midr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100324
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100325#define read_mpidr() read_mpidr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100326
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100327#define read_scr() read_scr_el3()
328#define write_scr(_v) write_scr_el3(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100329
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100330#define read_hcr() read_hcr_el2()
331#define write_hcr(_v) write_hcr_el2(_v)
Sandrine Bailleux25232af2014-05-09 11:23:11 +0100332
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100333#define read_cpacr() read_cpacr_el1()
334#define write_cpacr(_v) write_cpacr_el1(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100335
Achin Gupta4f6ad662013-10-25 09:08:21 +0100336#endif /* __ARCH_HELPERS_H__ */