blob: 46e20502fbef7637889c19c29322c7abd77a48ba [file] [log] [blame]
Rex-BC Chen749b2112021-09-28 11:24:09 +08001#
2# Copyright (c) 2021, MediaTek Inc. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7MTK_PLAT := plat/mediatek
8MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
9
10PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
Rex-BC Chend24c05d2021-10-06 18:55:53 +080011 -I${MTK_PLAT}/common/drivers/timer/ \
Penny Janfb70fb42021-10-03 10:11:04 +080012 -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
Rex-BC Chen749b2112021-09-28 11:24:09 +080013 -I${MTK_PLAT_SOC}/include/
14
15include drivers/arm/gic/v3/gicv3.mk
16include lib/xlat_tables_v2/xlat_tables.mk
17
18PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \
19 ${XLAT_TABLES_LIB_SRCS} \
20 plat/common/aarch64/crash_console_helpers.S \
21 plat/common/plat_psci_common.c
22
23
24BL31_SOURCES += common/desc_image_load.c \
25 drivers/ti/uart/aarch64/16550_console.S \
26 lib/bl_aux_params/bl_aux_params.c \
27 lib/cpus/aarch64/cortex_a55.S \
28 lib/cpus/aarch64/cortex_a76.S \
29 plat/common/plat_gicv3.c \
30 ${MTK_PLAT}/common/mtk_plat_common.c \
31 ${MTK_PLAT}/common/params_setup.c \
Rex-BC Chend24c05d2021-10-06 18:55:53 +080032 ${MTK_PLAT}/common/drivers/timer/mt_timer.c \
Rex-BC Chen749b2112021-09-28 11:24:09 +080033 ${MTK_PLAT_SOC}/aarch64/platform_common.c \
34 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
35 ${MTK_PLAT_SOC}/bl31_plat_setup.c \
Penny Janfb70fb42021-10-03 10:11:04 +080036 ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
Rex-BC Chen749b2112021-09-28 11:24:09 +080037 ${MTK_PLAT_SOC}/plat_pm.c \
38 ${MTK_PLAT_SOC}/plat_topology.c
39
40# Configs for A76 and A55
41HW_ASSISTED_COHERENCY := 1
42USE_COHERENT_MEM := 0
43CTX_INCLUDE_AARCH32_REGS := 0
44ERRATA_A55_1530923 := 1
45ERRATA_A55_1221012 := 1
46
47# indicate the reset vector address can be programmed
48PROGRAMMABLE_RESET_ADDRESS := 1
49
50COLD_BOOT_SINGLE_CPU := 1
51
52MACH_MT8186 := 1
53$(eval $(call add_define,MACH_MT8186))
54
55include lib/coreboot/coreboot.mk