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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
Jay Buddhabhatti6a44ad02023-02-28 01:23:04 -08003 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05304 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef PLATFORM_DEF_H
9#define PLATFORM_DEF_H
10
11#include <arch.h>
Tejas Patel0a2f9ad2018-12-14 00:55:30 -080012#include "versal_def.h"
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053013
14/*******************************************************************************
15 * Generic platform constants
16 ******************************************************************************/
17
18/* Size of cacheable stacks */
Venkatesh Yadav Abbarapua0657d92022-07-20 09:03:22 +053019#define PLATFORM_STACK_SIZE U(0x440)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053020
Deepika Bhavnanib16bada2019-12-13 10:53:56 -060021#define PLATFORM_CORE_COUNT U(2)
Abhyuday Godhasara589afa52021-08-11 06:15:13 -070022#define PLAT_MAX_PWR_LVL U(1)
23#define PLAT_MAX_RET_STATE U(1)
24#define PLAT_MAX_OFF_STATE U(2)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053025
26/*******************************************************************************
27 * BL31 specific defines.
28 ******************************************************************************/
29/*
30 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
31 * present). BL31_BASE is calculated using the current BL31 debug size plus a
32 * little space for growth.
33 */
34#ifndef VERSAL_ATF_MEM_BASE
Abhyuday Godhasara589afa52021-08-11 06:15:13 -070035# define BL31_BASE U(0xfffe0000)
Ilias Apalodimascc3e7392023-05-23 14:46:48 +030036# define BL31_LIMIT U(0x100000000)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053037#else
Prasad Kummariedfc0c22023-10-30 14:12:14 +053038# define BL31_BASE U(VERSAL_ATF_MEM_BASE)
39# define BL31_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053040# ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
Prasad Kummariedfc0c22023-10-30 14:12:14 +053041# define BL31_PROGBITS_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053042# endif
43#endif
44
45/*******************************************************************************
46 * BL32 specific defines.
47 ******************************************************************************/
48#ifndef VERSAL_BL32_MEM_BASE
Abhyuday Godhasara589afa52021-08-11 06:15:13 -070049# define BL32_BASE U(0x60000000)
Ilias Apalodimascc3e7392023-05-23 14:46:48 +030050# define BL32_LIMIT U(0x80000000)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053051#else
Prasad Kummariedfc0c22023-10-30 14:12:14 +053052# define BL32_BASE U(VERSAL_BL32_MEM_BASE)
53# define BL32_LIMIT U(VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053054#endif
55
56/*******************************************************************************
57 * BL33 specific defines.
58 ******************************************************************************/
59#ifndef PRELOADED_BL33_BASE
Abhyuday Godhasara589afa52021-08-11 06:15:13 -070060# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053061#else
Prasad Kummariedfc0c22023-10-30 14:12:14 +053062# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053063#endif
64
65/*******************************************************************************
66 * TSP specific defines.
67 ******************************************************************************/
68#define TSP_SEC_MEM_BASE BL32_BASE
Ilias Apalodimascc3e7392023-05-23 14:46:48 +030069#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053070
71/* ID of the secure physical generic timer interrupt used by the TSP */
72#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
73
74/*******************************************************************************
75 * Platform specific page table and MMU setup constants
76 ******************************************************************************/
77#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
78#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
Amit Nagal3a7d3042023-07-10 10:32:15 +053079
80#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
81
Amit Nagal64e41ba2023-08-29 02:44:58 -120082#define PLAT_OCM_BASE U(0xFFFE0000)
Amit Nagal3a7d3042023-07-10 10:32:15 +053083#define PLAT_OCM_LIMIT U(0xFFFFFFFF)
84
85#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT))
86
87#ifndef MAX_MMAP_REGIONS
88#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
89#define MAX_MMAP_REGIONS 9
90#else
Tejas Patel54d13192019-02-27 18:44:55 +053091#define MAX_MMAP_REGIONS 8
Amit Nagal3a7d3042023-07-10 10:32:15 +053092#endif
93#endif
94
95#ifndef MAX_XLAT_TABLES
96#if !IS_TFA_IN_OCM(BL31_BASE)
97#define MAX_XLAT_TABLES 9
98#else
99#define MAX_XLAT_TABLES 5
100#endif
101#endif
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530102
103#define CACHE_WRITEBACK_SHIFT 6
104#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
105
Jay Buddhabhatti6a44ad02023-02-28 01:23:04 -0800106#define PLAT_GICD_BASE_VALUE U(0xF9000000)
107#define PLAT_GICR_BASE_VALUE U(0xF9080000)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530108
109/*
110 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
111 * terminology. On a GICv2 system or mode, the lists will be merged and treated
112 * as Group 0 interrupts.
113 */
114#define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER
115#define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER
Abhyuday Godhasara589afa52021-08-11 06:15:13 -0700116#define PLAT_VERSAL_IPI_IRQ U(62)
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530117
118#define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
119 INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
120 GIC_INTR_CFG_LEVEL)
121
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530122#define PLAT_VERSAL_G0_IRQ_PROPS(grp) \
123 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
124 GIC_INTR_CFG_EDGE), \
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530125
Jay Buddhabhattia63b3542023-02-28 02:22:02 -0800126#define IRQ_MAX 142U
127
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530128#endif /* PLATFORM_DEF_H */