Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame^] | 2 | * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. |
Jay Buddhabhatti | 6a44ad0 | 2023-02-28 01:23:04 -0800 | [diff] [blame] | 3 | * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLATFORM_DEF_H |
| 9 | #define PLATFORM_DEF_H |
| 10 | |
| 11 | #include <arch.h> |
Tejas Patel | 0a2f9ad | 2018-12-14 00:55:30 -0800 | [diff] [blame] | 12 | #include "versal_def.h" |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 13 | |
| 14 | /******************************************************************************* |
| 15 | * Generic platform constants |
| 16 | ******************************************************************************/ |
| 17 | |
| 18 | /* Size of cacheable stacks */ |
Venkatesh Yadav Abbarapu | a0657d9 | 2022-07-20 09:03:22 +0530 | [diff] [blame] | 19 | #define PLATFORM_STACK_SIZE U(0x440) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 20 | |
Deepika Bhavnani | b16bada | 2019-12-13 10:53:56 -0600 | [diff] [blame] | 21 | #define PLATFORM_CORE_COUNT U(2) |
Abhyuday Godhasara | 589afa5 | 2021-08-11 06:15:13 -0700 | [diff] [blame] | 22 | #define PLAT_MAX_PWR_LVL U(1) |
| 23 | #define PLAT_MAX_RET_STATE U(1) |
| 24 | #define PLAT_MAX_OFF_STATE U(2) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 25 | |
| 26 | /******************************************************************************* |
| 27 | * BL31 specific defines. |
| 28 | ******************************************************************************/ |
| 29 | /* |
| 30 | * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if |
| 31 | * present). BL31_BASE is calculated using the current BL31 debug size plus a |
| 32 | * little space for growth. |
| 33 | */ |
| 34 | #ifndef VERSAL_ATF_MEM_BASE |
Abhyuday Godhasara | 589afa5 | 2021-08-11 06:15:13 -0700 | [diff] [blame] | 35 | # define BL31_BASE U(0xfffe0000) |
| 36 | # define BL31_LIMIT U(0xffffffff) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 37 | #else |
| 38 | # define BL31_BASE (VERSAL_ATF_MEM_BASE) |
| 39 | # define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE - 1) |
| 40 | # ifdef VERSAL_ATF_MEM_PROGBITS_SIZE |
| 41 | # define BL31_PROGBITS_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE - 1) |
| 42 | # endif |
| 43 | #endif |
| 44 | |
| 45 | /******************************************************************************* |
| 46 | * BL32 specific defines. |
| 47 | ******************************************************************************/ |
| 48 | #ifndef VERSAL_BL32_MEM_BASE |
Abhyuday Godhasara | 589afa5 | 2021-08-11 06:15:13 -0700 | [diff] [blame] | 49 | # define BL32_BASE U(0x60000000) |
| 50 | # define BL32_LIMIT U(0x7fffffff) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 51 | #else |
| 52 | # define BL32_BASE (VERSAL_BL32_MEM_BASE) |
| 53 | # define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE - 1) |
| 54 | #endif |
| 55 | |
| 56 | /******************************************************************************* |
| 57 | * BL33 specific defines. |
| 58 | ******************************************************************************/ |
| 59 | #ifndef PRELOADED_BL33_BASE |
Abhyuday Godhasara | 589afa5 | 2021-08-11 06:15:13 -0700 | [diff] [blame] | 60 | # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 61 | #else |
Venkatesh Yadav Abbarapu | 9156ffd | 2020-01-22 21:23:20 -0700 | [diff] [blame] | 62 | # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 63 | #endif |
| 64 | |
| 65 | /******************************************************************************* |
| 66 | * TSP specific defines. |
| 67 | ******************************************************************************/ |
| 68 | #define TSP_SEC_MEM_BASE BL32_BASE |
| 69 | #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) |
| 70 | |
| 71 | /* ID of the secure physical generic timer interrupt used by the TSP */ |
| 72 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 73 | |
| 74 | /******************************************************************************* |
| 75 | * Platform specific page table and MMU setup constants |
| 76 | ******************************************************************************/ |
| 77 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) |
| 78 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) |
Tejas Patel | 54d1319 | 2019-02-27 18:44:55 +0530 | [diff] [blame] | 79 | #define MAX_MMAP_REGIONS 8 |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 80 | #define MAX_XLAT_TABLES 5 |
| 81 | |
| 82 | #define CACHE_WRITEBACK_SHIFT 6 |
| 83 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 84 | |
Jay Buddhabhatti | 6a44ad0 | 2023-02-28 01:23:04 -0800 | [diff] [blame] | 85 | #define PLAT_GICD_BASE_VALUE U(0xF9000000) |
| 86 | #define PLAT_GICR_BASE_VALUE U(0xF9080000) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 87 | |
| 88 | /* |
| 89 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 90 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 91 | * as Group 0 interrupts. |
| 92 | */ |
| 93 | #define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER |
| 94 | #define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER |
Abhyuday Godhasara | 589afa5 | 2021-08-11 06:15:13 -0700 | [diff] [blame] | 95 | #define PLAT_VERSAL_IPI_IRQ U(62) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 96 | |
| 97 | #define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \ |
| 98 | INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 99 | GIC_INTR_CFG_LEVEL) |
| 100 | |
Shubhrajyoti Datta | abf6122 | 2021-03-17 23:01:17 +0530 | [diff] [blame] | 101 | #define PLAT_VERSAL_G0_IRQ_PROPS(grp) \ |
| 102 | INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 103 | GIC_INTR_CFG_EDGE), \ |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 104 | |
Jay Buddhabhatti | a63b354 | 2023-02-28 02:22:02 -0800 | [diff] [blame] | 105 | #define IRQ_MAX 142U |
| 106 | |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 107 | #endif /* PLATFORM_DEF_H */ |