blob: 06434f9e5ddbaccc6a72d68c5fa1912c2c95f0f1 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewb911cc72017-02-13 12:46:28 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#ifndef __PSCI_H__
8#define __PSCI_H__
9
Soby Mathew523d6332015-01-08 18:02:19 +000010#include <bakery_lock.h>
Soby Mathew89256b82016-09-13 14:19:08 +010011#include <bl_common.h>
Soby Mathew981487a2015-07-13 14:10:57 +010012#include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */
13#if ENABLE_PLAT_COMPAT
14#include <psci_compat.h>
15#endif
Soby Mathewb911cc72017-02-13 12:46:28 +000016#include <psci_lib.h> /* To maintain compatibility for SPDs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070017#include <utils_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010018
Achin Gupta4f6ad662013-10-25 09:08:21 +010019/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000020 * Number of power domains whose state this PSCI implementation can track
Soby Mathew523d6332015-01-08 18:02:19 +000021 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010022#ifdef PLAT_NUM_PWR_DOMAINS
23#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS
Soby Mathew523d6332015-01-08 18:02:19 +000024#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -070025#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT)
Soby Mathew523d6332015-01-08 18:02:19 +000026#endif
27
Soby Mathew981487a2015-07-13 14:10:57 +010028#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \
29 PLATFORM_CORE_COUNT)
30
31/* This is the power level corresponding to a CPU */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define PSCI_CPU_PWR_LVL (0)
Soby Mathew981487a2015-07-13 14:10:57 +010033
34/*
35 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND
36 * uses the old power_state parameter format which has 2 bits to specify the
37 * power level, this constant is defined to be 3.
38 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070039#define PSCI_MAX_PWR_LVL U(3)
Soby Mathew981487a2015-07-13 14:10:57 +010040
Soby Mathew523d6332015-01-08 18:02:19 +000041/*******************************************************************************
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +000042 * Defines for runtime services function ids
Achin Gupta4f6ad662013-10-25 09:08:21 +010043 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070044#define PSCI_VERSION U(0x84000000)
45#define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001)
46#define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001)
47#define PSCI_CPU_OFF U(0x84000002)
48#define PSCI_CPU_ON_AARCH32 U(0x84000003)
49#define PSCI_CPU_ON_AARCH64 U(0xc4000003)
50#define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004)
51#define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004)
52#define PSCI_MIG_AARCH32 U(0x84000005)
53#define PSCI_MIG_AARCH64 U(0xc4000005)
54#define PSCI_MIG_INFO_TYPE U(0x84000006)
55#define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007)
56#define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007)
57#define PSCI_SYSTEM_OFF U(0x84000008)
58#define PSCI_SYSTEM_RESET U(0x84000009)
59#define PSCI_FEATURES U(0x8400000A)
60#define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d)
61#define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d)
62#define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E)
63#define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E)
64#define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010)
65#define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010)
66#define PSCI_STAT_COUNT_AARCH32 U(0x84000011)
67#define PSCI_STAT_COUNT_AARCH64 U(0xc4000011)
Roberto Vargasb820ad02017-07-26 09:23:09 +010068#define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012)
69#define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012)
Roberto Vargas0a4c2612017-08-03 08:16:16 +010070#define PSCI_MEM_PROTECT U(0x84000013)
71#define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014)
72#define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014)
Soby Mathew6cdddaf2015-01-07 11:10:22 +000073
74/* Macro to help build the psci capabilities bitfield */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070075#define define_psci_cap(x) (U(1) << (x & U(0x1f)))
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000077/*
Juan Castillo4dc4a472014-08-12 11:17:06 +010078 * Number of PSCI calls (above) implemented
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000079 */
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010080#if ENABLE_PSCI_STAT
Varun Wadekarc6a11f62017-05-25 18:04:48 -070081#define PSCI_NUM_CALLS U(22)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010082#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -070083#define PSCI_NUM_CALLS U(18)
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010084#endif
Jeenu Viswambharan1814a3e2014-02-28 10:08:33 +000085
Soby Mathewd0194872016-04-29 19:01:30 +010086/* The macros below are used to identify PSCI calls from the SMC function ID */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070087#define PSCI_FID_MASK U(0xffe0)
88#define PSCI_FID_VALUE U(0)
Soby Mathewd0194872016-04-29 19:01:30 +010089#define is_psci_fid(_fid) \
90 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE)
91
Achin Gupta4f6ad662013-10-25 09:08:21 +010092/*******************************************************************************
93 * PSCI Migrate and friends
94 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070095#define PSCI_TOS_UP_MIG_CAP U(0)
96#define PSCI_TOS_NOT_UP_MIG_CAP U(1)
97#define PSCI_TOS_NOT_PRESENT_MP U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010098
99/*******************************************************************************
100 * PSCI CPU_SUSPEND 'power_state' parameter specific defines
101 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700102#define PSTATE_ID_SHIFT U(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103
Soby Mathew981487a2015-07-13 14:10:57 +0100104#if PSCI_EXTENDED_STATE_ID
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700105#define PSTATE_VALID_MASK U(0xB0000000)
106#define PSTATE_TYPE_SHIFT U(30)
107#define PSTATE_ID_MASK U(0xfffffff)
Soby Mathew981487a2015-07-13 14:10:57 +0100108#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700109#define PSTATE_VALID_MASK U(0xFCFE0000)
110#define PSTATE_TYPE_SHIFT U(16)
111#define PSTATE_PWR_LVL_SHIFT U(24)
112#define PSTATE_ID_MASK U(0xffff)
113#define PSTATE_PWR_LVL_MASK U(0x3)
Soby Mathew981487a2015-07-13 14:10:57 +0100114
115#define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \
116 PSTATE_PWR_LVL_MASK)
117#define psci_make_powerstate(state_id, type, pwrlvl) \
118 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\
119 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\
120 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT)
121#endif /* __PSCI_EXTENDED_STATE_ID__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700123#define PSTATE_TYPE_STANDBY U(0x0)
124#define PSTATE_TYPE_POWERDOWN U(0x1)
125#define PSTATE_TYPE_MASK U(0x1)
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000126
Soby Mathew96168382014-12-17 14:47:57 +0000127#define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \
Soby Mathew74e52a72014-10-02 16:56:51 +0100128 PSTATE_ID_MASK)
Soby Mathew96168382014-12-17 14:47:57 +0000129#define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \
Soby Mathew74e52a72014-10-02 16:56:51 +0100130 PSTATE_TYPE_MASK)
Soby Mathew981487a2015-07-13 14:10:57 +0100131#define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132
133/*******************************************************************************
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000134 * PSCI CPU_FEATURES feature flag specific defines
135 ******************************************************************************/
136/* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700137#define FF_PSTATE_SHIFT U(1)
138#define FF_PSTATE_ORIG U(0)
139#define FF_PSTATE_EXTENDED U(1)
Soby Mathew981487a2015-07-13 14:10:57 +0100140#if PSCI_EXTENDED_STATE_ID
141#define FF_PSTATE FF_PSTATE_EXTENDED
142#else
143#define FF_PSTATE FF_PSTATE_ORIG
144#endif
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000145
146/* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700147#define FF_MODE_SUPPORT_SHIFT U(0)
148#define FF_SUPPORTS_OS_INIT_MODE U(1)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000149
150/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151 * PSCI version
152 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700153#define PSCI_MAJOR_VER (U(1) << 16)
Roberto Vargasffb34d02017-09-11 09:11:58 +0100154#define PSCI_MINOR_VER U(0x1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100155
156/*******************************************************************************
157 * PSCI error codes
158 ******************************************************************************/
159#define PSCI_E_SUCCESS 0
160#define PSCI_E_NOT_SUPPORTED -1
161#define PSCI_E_INVALID_PARAMS -2
162#define PSCI_E_DENIED -3
163#define PSCI_E_ALREADY_ON -4
164#define PSCI_E_ON_PENDING -5
165#define PSCI_E_INTERN_FAIL -6
166#define PSCI_E_NOT_PRESENT -7
167#define PSCI_E_DISABLED -8
Soby Mathewf1f97a12015-07-15 12:13:26 +0100168#define PSCI_E_INVALID_ADDRESS -9
Achin Gupta4f6ad662013-10-25 09:08:21 +0100169
Soby Mathew011ca182015-07-29 17:05:03 +0100170#define PSCI_INVALID_MPIDR ~((u_register_t)0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171
Roberto Vargasb820ad02017-07-26 09:23:09 +0100172/*
173 * SYSTEM_RESET2 macros
174 */
175#define PSCI_RESET2_TYPE_VENDOR_SHIFT 31
176#define PSCI_RESET2_TYPE_VENDOR (1U << PSCI_RESET2_TYPE_VENDOR_SHIFT)
177#define PSCI_RESET2_TYPE_ARCH (0U << PSCI_RESET2_TYPE_VENDOR_SHIFT)
178#define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | 0)
179
Soby Mathew981487a2015-07-13 14:10:57 +0100180#ifndef __ASSEMBLY__
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181
Soby Mathew981487a2015-07-13 14:10:57 +0100182#include <stdint.h>
183#include <types.h>
184
185/*
186 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified
187 * CPU. The definitions of these states can be found in Section 5.7.1 in the
188 * PSCI specification (ARM DEN 0022C).
189 */
190typedef enum {
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700191 AFF_STATE_ON = U(0),
192 AFF_STATE_OFF = U(1),
193 AFF_STATE_ON_PENDING = U(2)
Soby Mathew981487a2015-07-13 14:10:57 +0100194} aff_info_state_t;
195
196/*
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100197 * These are the power states reported by PSCI_NODE_HW_STATE API for the
198 * specified CPU. The definitions of these states can be found in Section 5.15.3
199 * of PSCI specification (ARM DEN 0022C).
200 */
201typedef enum {
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700202 HW_ON = U(0),
203 HW_OFF = U(1),
204 HW_STANDBY = U(2)
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100205} node_hw_state_t;
206
207/*
Soby Mathew981487a2015-07-13 14:10:57 +0100208 * Macro to represent invalid affinity level within PSCI.
209 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700210#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1))
Vikram Kanigirif100f412014-04-01 19:26:26 +0100211
Soby Mathew981487a2015-07-13 14:10:57 +0100212/*
213 * Type for representing the local power state at a particular level.
214 */
215typedef uint8_t plat_local_state_t;
216
217/* The local state macro used to represent RUN state. */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700218#define PSCI_LOCAL_STATE_RUN U(0)
Achin Gupta75f73672013-12-05 16:33:10 +0000219
Soby Mathew981487a2015-07-13 14:10:57 +0100220/*
221 * Macro to test whether the plat_local_state is RUN state
222 */
223#define is_local_state_run(plat_local_state) \
224 ((plat_local_state) == PSCI_LOCAL_STATE_RUN)
Vikram Kanigirif100f412014-04-01 19:26:26 +0100225
Soby Mathew981487a2015-07-13 14:10:57 +0100226/*
227 * Macro to test whether the plat_local_state is RETENTION state
228 */
229#define is_local_state_retn(plat_local_state) \
230 (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \
231 ((plat_local_state) <= PLAT_MAX_RET_STATE))
Vikram Kanigirif100f412014-04-01 19:26:26 +0100232
Soby Mathew981487a2015-07-13 14:10:57 +0100233/*
234 * Macro to test whether the plat_local_state is OFF state
235 */
236#define is_local_state_off(plat_local_state) \
237 (((plat_local_state) > PLAT_MAX_RET_STATE) && \
238 ((plat_local_state) <= PLAT_MAX_OFF_STATE))
Dan Handley2bd4ef22014-04-09 13:14:54 +0100239
Soby Mathew981487a2015-07-13 14:10:57 +0100240/*****************************************************************************
241 * This data structure defines the representation of the power state parameter
242 * for its exchange between the generic PSCI code and the platform port. For
243 * example, it is used by the platform port to specify the requested power
244 * states during a power management operation. It is used by the generic code to
245 * inform the platform about the target power states that each level should
246 * enter.
247 ****************************************************************************/
248typedef struct psci_power_state {
249 /*
250 * The pwr_domain_state[] stores the local power state at each level
251 * for the CPU.
252 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700253 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)];
Soby Mathew981487a2015-07-13 14:10:57 +0100254} psci_power_state_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100255
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100256/*******************************************************************************
257 * Structure used to store per-cpu information relevant to the PSCI service.
258 * It is populated in the per-cpu data array. In return we get a guarantee that
259 * this information will not reside on a cache line shared with another cpu.
260 ******************************************************************************/
261typedef struct psci_cpu_data {
Soby Mathew981487a2015-07-13 14:10:57 +0100262 /* State as seen by PSCI Affinity Info API */
263 aff_info_state_t aff_info_state;
Soby Mathew011ca182015-07-29 17:05:03 +0100264
Soby Mathew981487a2015-07-13 14:10:57 +0100265 /*
266 * Highest power level which takes part in a power management
267 * operation.
268 */
Soby Mathew011ca182015-07-29 17:05:03 +0100269 unsigned char target_pwrlvl;
270
Soby Mathew981487a2015-07-13 14:10:57 +0100271 /* The local power state of this CPU */
272 plat_local_state_t local_state;
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100273} psci_cpu_data_t;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100274
Achin Gupta4f6ad662013-10-25 09:08:21 +0100275/*******************************************************************************
276 * Structure populated by platform specific code to export routines which
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000277 * perform common low level power management functions
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100279typedef struct plat_psci_ops {
280 void (*cpu_standby)(plat_local_state_t cpu_state);
281 int (*pwr_domain_on)(u_register_t mpidr);
282 void (*pwr_domain_off)(const psci_power_state_t *target_state);
Varun Wadekarae87f4b2017-07-10 16:02:05 -0700283 void (*pwr_domain_suspend_pwrdown_early)(
284 const psci_power_state_t *target_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100285 void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
286 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
287 void (*pwr_domain_suspend_finish)(
288 const psci_power_state_t *target_state);
Soby Mathew6a816412016-04-27 14:46:28 +0100289 void (*pwr_domain_pwr_down_wfi)(
290 const psci_power_state_t *target_state) __dead2;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100291 void (*system_off)(void) __dead2;
292 void (*system_reset)(void) __dead2;
Soby Mathew981487a2015-07-13 14:10:57 +0100293 int (*validate_power_state)(unsigned int power_state,
294 psci_power_state_t *req_state);
Soby Mathew011ca182015-07-29 17:05:03 +0100295 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint);
Soby Mathew981487a2015-07-13 14:10:57 +0100296 void (*get_sys_suspend_power_state)(
297 psci_power_state_t *req_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100298 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
299 int pwrlvl);
300 int (*translate_power_state_by_mpidr)(u_register_t mpidr,
301 unsigned int power_state,
302 psci_power_state_t *output_state);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100303 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level);
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100304 int (*mem_protect_chk)(uintptr_t base, u_register_t length);
305 int (*read_mem_protect)(int *val);
306 int (*write_mem_protect)(int val);
Roberto Vargasb820ad02017-07-26 09:23:09 +0100307 int (*system_reset2)(int is_vendor,
308 int reset_type, u_register_t cookie);
Soby Mathew981487a2015-07-13 14:10:57 +0100309} plat_psci_ops_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310
311/*******************************************************************************
312 * Function & Data prototypes
313 ******************************************************************************/
Dan Handleya17fefa2014-05-14 12:38:32 +0100314unsigned int psci_version(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100315int psci_cpu_on(u_register_t target_cpu,
316 uintptr_t entrypoint,
317 u_register_t context_id);
318int psci_cpu_suspend(unsigned int power_state,
319 uintptr_t entrypoint,
320 u_register_t context_id);
321int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id);
322int psci_cpu_off(void);
323int psci_affinity_info(u_register_t target_affinity,
324 unsigned int lowest_affinity_level);
325int psci_migrate(u_register_t target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100326int psci_migrate_info_type(void);
327long psci_migrate_info_up_cpu(void);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100328int psci_node_hw_state(u_register_t target_cpu,
329 unsigned int power_level);
Soby Mathew011ca182015-07-29 17:05:03 +0100330int psci_features(unsigned int psci_fid);
Dan Handleya17fefa2014-05-14 12:38:32 +0100331void __dead2 psci_power_down_wfi(void);
Soby Mathewd0194872016-04-29 19:01:30 +0100332void psci_arch_setup(void);
333
334/*
335 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in
336 * AArch64.
337 */
338void psci_entrypoint(void) __deprecated;
339
Achin Gupta4f6ad662013-10-25 09:08:21 +0100340#endif /*__ASSEMBLY__*/
341
Achin Gupta4f6ad662013-10-25 09:08:21 +0100342#endif /* __PSCI_H__ */