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Soby Mathew991d42c2015-06-29 16:30:12 +01001/*
dp-arm66abfbe2017-01-31 13:01:04 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathew991d42c2015-06-29 16:30:12 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew991d42c2015-06-29 16:30:12 +01005 */
6
7#include <assert.h>
8#include <bl_common.h>
9#include <arch.h>
10#include <arch_helpers.h>
11#include <context.h>
12#include <context_mgmt.h>
13#include <cpu_data.h>
14#include <debug.h>
15#include <platform.h>
dp-arm3cac7862016-09-19 11:18:44 +010016#include <pmf.h>
17#include <runtime_instr.h>
Soby Mathew991d42c2015-06-29 16:30:12 +010018#include <stddef.h>
19#include "psci_private.h"
20
Soby Mathew991d42c2015-06-29 16:30:12 +010021/*******************************************************************************
Soby Mathew85dbf5a2015-04-07 12:16:56 +010022 * This function does generic and platform specific operations after a wake-up
23 * from standby/retention states at multiple power levels.
Soby Mathew991d42c2015-06-29 16:30:12 +010024 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +010025static void psci_suspend_to_standby_finisher(unsigned int cpu_idx,
Soby Mathew85dbf5a2015-04-07 12:16:56 +010026 unsigned int end_pwrlvl)
Soby Mathew991d42c2015-06-29 16:30:12 +010027{
Achin Gupta9b2bf252016-06-28 16:46:15 +010028 psci_power_state_t state_info;
29
Soby Mathew85dbf5a2015-04-07 12:16:56 +010030 psci_acquire_pwr_domain_locks(end_pwrlvl,
31 cpu_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010032
Soby Mathew85dbf5a2015-04-07 12:16:56 +010033 /*
Achin Gupta9b2bf252016-06-28 16:46:15 +010034 * Find out which retention states this CPU has exited from until the
35 * 'end_pwrlvl'. The exit retention state could be deeper than the entry
36 * state as a result of state coordination amongst other CPUs post wfi.
37 */
38 psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
39
40 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +010041 * Plat. management: Allow the platform to do operations
42 * on waking up from retention.
43 */
Achin Gupta9b2bf252016-06-28 16:46:15 +010044 psci_plat_pm_ops->pwr_domain_suspend_finish(&state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +010045
Soby Mathew85dbf5a2015-04-07 12:16:56 +010046 /*
47 * Set the requested and target state of this CPU and all the higher
48 * power domain levels for this CPU to run.
49 */
50 psci_set_pwr_domains_to_run(end_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010051
Soby Mathew85dbf5a2015-04-07 12:16:56 +010052 psci_release_pwr_domain_locks(end_pwrlvl,
53 cpu_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010054}
55
56/*******************************************************************************
Soby Mathew85dbf5a2015-04-07 12:16:56 +010057 * This function does generic and platform specific suspend to power down
58 * operations.
Soby Mathew991d42c2015-06-29 16:30:12 +010059 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010060static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl,
Soby Mathew85dbf5a2015-04-07 12:16:56 +010061 entry_point_info_t *ep,
62 psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +010063{
Achin Gupta9a0ff9b2015-09-07 20:43:27 +010064 unsigned int max_off_lvl = psci_find_max_off_lvl(state_info);
65
Soby Mathew85dbf5a2015-04-07 12:16:56 +010066 /* Save PSCI target power level for the suspend finisher handler */
67 psci_set_suspend_pwrlvl(end_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010068
Soby Mathew85dbf5a2015-04-07 12:16:56 +010069 /*
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +000070 * Flush the target power level as it might be accessed on power up with
Soby Mathew85dbf5a2015-04-07 12:16:56 +010071 * Data cache disabled.
72 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +000073 psci_flush_cpu_data(psci_svc_cpu_data.target_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010074
Soby Mathew85dbf5a2015-04-07 12:16:56 +010075 /*
76 * Call the cpu suspend handler registered by the Secure Payload
77 * Dispatcher to let it do any book-keeping. If the handler encounters an
78 * error, it's expected to assert within
79 */
80 if (psci_spd_pm && psci_spd_pm->svc_suspend)
Achin Gupta9a0ff9b2015-09-07 20:43:27 +010081 psci_spd_pm->svc_suspend(max_off_lvl);
Soby Mathew991d42c2015-06-29 16:30:12 +010082
Soby Mathew85dbf5a2015-04-07 12:16:56 +010083 /*
84 * Store the re-entry information for the non-secure world.
85 */
86 cm_init_my_context(ep);
Soby Mathew991d42c2015-06-29 16:30:12 +010087
dp-arm2d92de62016-11-15 13:25:30 +000088#if ENABLE_RUNTIME_INSTRUMENTATION
89
90 /*
91 * Flush cache line so that even if CPU power down happens
92 * the timestamp update is reflected in memory.
93 */
94 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
95 RT_INSTR_ENTER_CFLUSH,
96 PMF_CACHE_MAINT);
97#endif
98
Soby Mathew85dbf5a2015-04-07 12:16:56 +010099 /*
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000100 * Arch. management. Initiate power down sequence.
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100101 * TODO : Introduce a mechanism to query the cache level to flush
102 * and the cpu-ops power down to perform from the platform.
103 */
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000104 psci_do_pwrdown_sequence(max_off_lvl);
dp-arm2d92de62016-11-15 13:25:30 +0000105
106#if ENABLE_RUNTIME_INSTRUMENTATION
107 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
108 RT_INSTR_EXIT_CFLUSH,
109 PMF_NO_CACHE_MAINT);
110#endif
Soby Mathew991d42c2015-06-29 16:30:12 +0100111}
112
113/*******************************************************************************
Soby Mathew991d42c2015-06-29 16:30:12 +0100114 * Top level handler which is called when a cpu wants to suspend its execution.
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100115 * It is assumed that along with suspending the cpu power domain, power domains
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100116 * at higher levels until the target power level will be suspended as well. It
117 * coordinates with the platform to negotiate the target state for each of
118 * the power domain level till the target power domain level. It then performs
119 * generic, architectural, platform setup and state management required to
120 * suspend that power domain level and power domain levels below it.
121 * e.g. For a cpu that's to be suspended, it could mean programming the
122 * power controller whereas for a cluster that's to be suspended, it will call
123 * the platform specific code which will disable coherency at the interconnect
124 * level if the cpu is the last in the cluster and also the program the power
125 * controller.
Soby Mathew991d42c2015-06-29 16:30:12 +0100126 *
127 * All the required parameter checks are performed at the beginning and after
Soby Mathew6b8b3022015-06-30 11:00:24 +0100128 * the state transition has been done, no further error is expected and it is
129 * not possible to undo any of the actions taken beyond that point.
Soby Mathew991d42c2015-06-29 16:30:12 +0100130 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100131void psci_cpu_suspend_start(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100132 unsigned int end_pwrlvl,
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100133 psci_power_state_t *state_info,
134 unsigned int is_power_down_state)
Soby Mathew991d42c2015-06-29 16:30:12 +0100135{
136 int skip_wfi = 0;
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100137 unsigned int idx = plat_my_core_pos();
Soby Mathew991d42c2015-06-29 16:30:12 +0100138
139 /*
140 * This function must only be called on platforms where the
141 * CPU_SUSPEND platform hooks have been implemented.
142 */
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100143 assert(psci_plat_pm_ops->pwr_domain_suspend &&
144 psci_plat_pm_ops->pwr_domain_suspend_finish);
Soby Mathew991d42c2015-06-29 16:30:12 +0100145
146 /*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100147 * This function acquires the lock corresponding to each power
Soby Mathew991d42c2015-06-29 16:30:12 +0100148 * level so that by the time all locks are taken, the system topology
149 * is snapshot and state management can be done safely.
150 */
Soby Mathew9d754f62015-04-08 17:42:06 +0100151 psci_acquire_pwr_domain_locks(end_pwrlvl,
152 idx);
Soby Mathew991d42c2015-06-29 16:30:12 +0100153
154 /*
155 * We check if there are any pending interrupts after the delay
156 * introduced by lock contention to increase the chances of early
157 * detection that a wake-up interrupt has fired.
158 */
159 if (read_isr_el1()) {
160 skip_wfi = 1;
161 goto exit;
162 }
163
164 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100165 * This function is passed the requested state info and
166 * it returns the negotiated state info for each power level upto
167 * the end level specified.
Soby Mathew991d42c2015-06-29 16:30:12 +0100168 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100169 psci_do_state_coordination(end_pwrlvl, state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100170
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100171#if ENABLE_PSCI_STAT
172 /* Update the last cpu for each level till end_pwrlvl */
173 psci_stats_update_pwr_down(end_pwrlvl, state_info);
174#endif
175
Sandrine Bailleux574d6852015-06-11 10:46:48 +0100176 if (is_power_down_state)
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100177 psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100178
Soby Mathew6b8b3022015-06-30 11:00:24 +0100179 /*
180 * Plat. management: Allow the platform to perform the
181 * necessary actions to turn off this cpu e.g. set the
182 * platform defined mailbox with the psci entrypoint,
183 * program the power controller etc.
184 */
Sandrine Bailleux574d6852015-06-11 10:46:48 +0100185 psci_plat_pm_ops->pwr_domain_suspend(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100186
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100187#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000188 plat_psci_stat_accounting_start(state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100189#endif
190
Soby Mathew991d42c2015-06-29 16:30:12 +0100191exit:
192 /*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100193 * Release the locks corresponding to each power level in the
Soby Mathew991d42c2015-06-29 16:30:12 +0100194 * reverse order to which they were acquired.
195 */
Soby Mathew9d754f62015-04-08 17:42:06 +0100196 psci_release_pwr_domain_locks(end_pwrlvl,
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100197 idx);
198 if (skip_wfi)
199 return;
200
Soby Mathew6a816412016-04-27 14:46:28 +0100201 if (is_power_down_state) {
dp-arm3cac7862016-09-19 11:18:44 +0100202#if ENABLE_RUNTIME_INSTRUMENTATION
203
204 /*
205 * Update the timestamp with cache off. We assume this
206 * timestamp can only be read from the current CPU and the
207 * timestamp cache line will be flushed before return to
208 * normal world on wakeup.
209 */
210 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
211 RT_INSTR_ENTER_HW_LOW_PWR,
212 PMF_NO_CACHE_MAINT);
213#endif
214
Soby Mathew6a816412016-04-27 14:46:28 +0100215 /* The function calls below must not return */
216 if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi)
217 psci_plat_pm_ops->pwr_domain_pwr_down_wfi(state_info);
218 else
219 psci_power_down_wfi();
220 }
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100221
dp-arm3cac7862016-09-19 11:18:44 +0100222#if ENABLE_RUNTIME_INSTRUMENTATION
223 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
224 RT_INSTR_ENTER_HW_LOW_PWR,
225 PMF_NO_CACHE_MAINT);
226#endif
227
dp-arm37ce1502017-01-31 13:03:00 +0000228#if ENABLE_PSCI_STAT
229 plat_psci_stat_accounting_start(state_info);
230#endif
231
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100232 /*
233 * We will reach here if only retention/standby states have been
234 * requested at multiple power levels. This means that the cpu
235 * context will be preserved.
236 */
237 wfi();
238
dp-arm37ce1502017-01-31 13:03:00 +0000239#if ENABLE_PSCI_STAT
240 plat_psci_stat_accounting_stop(state_info);
241 psci_stats_update_pwr_up(end_pwrlvl, state_info);
242#endif
243
dp-arm3cac7862016-09-19 11:18:44 +0100244#if ENABLE_RUNTIME_INSTRUMENTATION
245 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
246 RT_INSTR_EXIT_HW_LOW_PWR,
247 PMF_NO_CACHE_MAINT);
248#endif
249
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100250 /*
251 * After we wake up from context retaining suspend, call the
252 * context retaining suspend finisher.
253 */
Achin Gupta9b2bf252016-06-28 16:46:15 +0100254 psci_suspend_to_standby_finisher(idx, end_pwrlvl);
Soby Mathew991d42c2015-06-29 16:30:12 +0100255}
256
257/*******************************************************************************
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100258 * The following functions finish an earlier suspend request. They
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100259 * are called by the common finisher routine in psci_common.c. The `state_info`
260 * is the psci_power_state from which this CPU has woken up from.
Soby Mathew991d42c2015-06-29 16:30:12 +0100261 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100262void psci_cpu_suspend_finish(unsigned int cpu_idx,
263 psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +0100264{
Antonio Nino Diaz391a76e2016-05-18 16:53:31 +0100265 unsigned int counter_freq;
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100266 unsigned int max_off_lvl;
Soby Mathew991d42c2015-06-29 16:30:12 +0100267
Soby Mathew991d42c2015-06-29 16:30:12 +0100268 /* Ensure we have been woken up from a suspended state */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100269 assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\
270 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]));
Soby Mathew991d42c2015-06-29 16:30:12 +0100271
272 /*
273 * Plat. management: Perform the platform specific actions
274 * before we change the state of the cpu e.g. enabling the
275 * gic or zeroing the mailbox register. If anything goes
276 * wrong then assert as there is no way to recover from this
277 * situation.
278 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100279 psci_plat_pm_ops->pwr_domain_suspend_finish(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100280
Soby Mathew043fe9c2017-04-10 22:35:42 +0100281#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000282 /* Arch. management: Enable the data cache, stack memory maintenance. */
Soby Mathew991d42c2015-06-29 16:30:12 +0100283 psci_do_pwrup_cache_maintenance();
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000284#endif
Soby Mathew991d42c2015-06-29 16:30:12 +0100285
286 /* Re-init the cntfrq_el0 register */
Antonio Nino Diaz391a76e2016-05-18 16:53:31 +0100287 counter_freq = plat_get_syscnt_freq2();
Soby Mathew991d42c2015-06-29 16:30:12 +0100288 write_cntfrq_el0(counter_freq);
289
290 /*
291 * Call the cpu suspend finish handler registered by the Secure Payload
292 * Dispatcher to let it do any bookeeping. If the handler encounters an
293 * error, it's expected to assert within
294 */
295 if (psci_spd_pm && psci_spd_pm->svc_suspend) {
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100296 max_off_lvl = psci_find_max_off_lvl(state_info);
297 assert (max_off_lvl != PSCI_INVALID_PWR_LVL);
298 psci_spd_pm->svc_suspend_finish(max_off_lvl);
Soby Mathew991d42c2015-06-29 16:30:12 +0100299 }
300
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100301 /* Invalidate the suspend level for the cpu */
Soby Mathew011ca182015-07-29 17:05:03 +0100302 psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL);
Soby Mathew991d42c2015-06-29 16:30:12 +0100303
304 /*
305 * Generic management: Now we just need to retrieve the
306 * information that we had stashed away during the suspend
307 * call to set this cpu on its way.
308 */
309 cm_prepare_el3_exit(NON_SECURE);
Soby Mathew991d42c2015-06-29 16:30:12 +0100310}