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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautier8f268c82020-02-26 13:39:44 +01002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Lionel Debieve7bd96f42019-09-03 12:22:23 +020022#include <stm32mp_auth.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010023#include <stm32mp_common.h>
24#include <stm32mp_dt.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010025#include <stm32mp_shres_helpers.h>
Yann Gautierc7374052019-06-04 18:02:37 +020026#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010027#include <stm32mp1_private.h>
28#endif
29
Yann Gautier4b0c72a2018-07-16 10:54:09 +020030/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020031 * CHIP ID
32 ******************************************************************************/
33#define STM32MP157C_PART_NB U(0x05000000)
34#define STM32MP157A_PART_NB U(0x05000001)
35#define STM32MP153C_PART_NB U(0x05000024)
36#define STM32MP153A_PART_NB U(0x05000025)
37#define STM32MP151C_PART_NB U(0x0500002E)
38#define STM32MP151A_PART_NB U(0x0500002F)
39
40#define STM32MP1_REV_B U(0x2000)
41
42/*******************************************************************************
43 * PACKAGE ID
44 ******************************************************************************/
45#define PKG_AA_LFBGA448 U(4)
46#define PKG_AB_LFBGA354 U(3)
47#define PKG_AC_TFBGA361 U(2)
48#define PKG_AD_TFBGA257 U(1)
49
50/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020051 * STM32MP1 memory map related constants
52 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020053#define STM32MP_ROM_BASE U(0x00000000)
54#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020055
Yann Gautiera2e2a302019-02-14 11:13:39 +010056#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
57#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020058
59/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +010060#define STM32MP_DDR_BASE U(0xC0000000)
61#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautierb3386f72019-04-19 09:41:01 +020062#ifdef AARCH32_SP_OPTEE
63#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
64#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
Yann Gautier8f268c82020-02-26 13:39:44 +010065#else
66#define STM32MP_DDR_S_SIZE U(0)
67#define STM32MP_DDR_SHMEM_SIZE U(0)
Yann Gautierb3386f72019-04-19 09:41:01 +020068#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020069
70/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -070071#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +020072enum ddr_type {
73 STM32MP_DDR3,
74 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +020075 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +020076};
77#endif
78
79/* Section used inside TF binaries */
Nicolas Le Bayon07084412019-09-27 11:05:31 +020080#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020081/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +010082#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020083
Yann Gautiera2e2a302019-02-14 11:13:39 +010084#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
85 STM32MP_PARAM_LOAD_SIZE + \
86 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020087
Yann Gautiera2e2a302019-02-14 11:13:39 +010088#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
89 (STM32MP_PARAM_LOAD_SIZE + \
90 STM32MP_HEADER_SIZE))
Yann Gautier4b0c72a2018-07-16 10:54:09 +020091
Yann Gautierb3386f72019-04-19 09:41:01 +020092#ifdef AARCH32_SP_OPTEE
93#define STM32MP_BL32_SIZE U(0)
94
95#define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE
96
97#define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
98 STM32MP_OPTEE_BASE)
99#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200100#if STACK_PROTECTOR_ENABLED
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200101#define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200102#else
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200103#define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200104#endif
Yann Gautierb3386f72019-04-19 09:41:01 +0200105#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200106
Yann Gautiera2e2a302019-02-14 11:13:39 +0100107#define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \
108 STM32MP_SYSRAM_SIZE - \
109 STM32MP_BL32_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200110
Yann Gautierb3386f72019-04-19 09:41:01 +0200111#ifdef AARCH32_SP_OPTEE
112#if STACK_PROTECTOR_ENABLED
Lionel Debieve402a46b2019-11-04 12:28:15 +0100113#define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */
Yann Gautierb3386f72019-04-19 09:41:01 +0200114#else
Lionel Debieve402a46b2019-11-04 12:28:15 +0100115#define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */
Yann Gautierb3386f72019-04-19 09:41:01 +0200116#endif
117#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200118#if STACK_PROTECTOR_ENABLED
Lionel Debieve402a46b2019-11-04 12:28:15 +0100119#define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200120#else
Lionel Debieve402a46b2019-11-04 12:28:15 +0100121#define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200122#endif
Yann Gautierb3386f72019-04-19 09:41:01 +0200123#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200124
Yann Gautiera2e2a302019-02-14 11:13:39 +0100125#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
126 STM32MP_BL2_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200127
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200128/* BL2 and BL32/sp_min require 4 tables */
129#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200130
131/*
132 * MAX_MMAP_REGIONS is usually:
133 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
134 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200135#if defined(IMAGE_BL2)
136 #define MAX_MMAP_REGIONS 11
137#endif
138#if defined(IMAGE_BL32)
139 #define MAX_MMAP_REGIONS 6
140#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200141
142/* DTB initialization value */
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200143#define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200144
Yann Gautiera2e2a302019-02-14 11:13:39 +0100145#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
146 STM32MP_DTB_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200147
Yann Gautiera2e2a302019-02-14 11:13:39 +0100148#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200149
Lionel Debieve402a46b2019-11-04 12:28:15 +0100150/* Define maximum page size for NAND devices */
151#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
152
153/*******************************************************************************
154 * STM32MP1 RAW partition offset for MTD devices
155 ******************************************************************************/
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200156#define STM32MP_NOR_BL33_OFFSET U(0x00080000)
157#ifdef AARCH32_SP_OPTEE
158#define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
159#define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
160#define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
161#endif
162
Lionel Debieve402a46b2019-11-04 12:28:15 +0100163#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
164#ifdef AARCH32_SP_OPTEE
165#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
166#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
167#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
168#endif
169
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200170/*******************************************************************************
171 * STM32MP1 device/io map related constants (used for MMU)
172 ******************************************************************************/
173#define STM32MP1_DEVICE1_BASE U(0x40000000)
174#define STM32MP1_DEVICE1_SIZE U(0x40000000)
175
176#define STM32MP1_DEVICE2_BASE U(0x80000000)
177#define STM32MP1_DEVICE2_SIZE U(0x40000000)
178
179/*******************************************************************************
180 * STM32MP1 RCC
181 ******************************************************************************/
182#define RCC_BASE U(0x50000000)
183
184/*******************************************************************************
185 * STM32MP1 PWR
186 ******************************************************************************/
187#define PWR_BASE U(0x50001000)
188
189/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100190 * STM32MP1 GPIO
191 ******************************************************************************/
192#define GPIOA_BASE U(0x50002000)
193#define GPIOB_BASE U(0x50003000)
194#define GPIOC_BASE U(0x50004000)
195#define GPIOD_BASE U(0x50005000)
196#define GPIOE_BASE U(0x50006000)
197#define GPIOF_BASE U(0x50007000)
198#define GPIOG_BASE U(0x50008000)
199#define GPIOH_BASE U(0x50009000)
200#define GPIOI_BASE U(0x5000A000)
201#define GPIOJ_BASE U(0x5000B000)
202#define GPIOK_BASE U(0x5000C000)
203#define GPIOZ_BASE U(0x54004000)
204#define GPIO_BANK_OFFSET U(0x1000)
205
206/* Bank IDs used in GPIO driver API */
207#define GPIO_BANK_A U(0)
208#define GPIO_BANK_B U(1)
209#define GPIO_BANK_C U(2)
210#define GPIO_BANK_D U(3)
211#define GPIO_BANK_E U(4)
212#define GPIO_BANK_F U(5)
213#define GPIO_BANK_G U(6)
214#define GPIO_BANK_H U(7)
215#define GPIO_BANK_I U(8)
216#define GPIO_BANK_J U(9)
217#define GPIO_BANK_K U(10)
218#define GPIO_BANK_Z U(25)
219
220#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
221
222/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200223 * STM32MP1 UART
224 ******************************************************************************/
225#define USART1_BASE U(0x5C000000)
226#define USART2_BASE U(0x4000E000)
227#define USART3_BASE U(0x4000F000)
228#define UART4_BASE U(0x40010000)
229#define UART5_BASE U(0x40011000)
230#define USART6_BASE U(0x44003000)
231#define UART7_BASE U(0x40018000)
232#define UART8_BASE U(0x40019000)
Yann Gautiera2e2a302019-02-14 11:13:39 +0100233#define STM32MP_UART_BAUDRATE U(115200)
Yann Gautier038bff22019-01-17 19:17:47 +0100234
235/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100236#define STM32MP_DEBUG_USART_BASE UART4_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100237/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100238#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100239#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
240#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
241#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
242#define DEBUG_UART_TX_GPIO_PORT 11
243#define DEBUG_UART_TX_GPIO_ALTERNATE 6
244#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
245#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
246#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
247#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200248
249/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200250 * STM32MP1 TZC (TZ400)
251 ******************************************************************************/
252#define STM32MP1_TZC_BASE U(0x5C006000)
253
254#define STM32MP1_TZC_A7_ID U(0)
Yann Gautiered342322019-02-15 17:33:27 +0100255#define STM32MP1_TZC_M4_ID U(1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200256#define STM32MP1_TZC_LCD_ID U(3)
257#define STM32MP1_TZC_GPU_ID U(4)
258#define STM32MP1_TZC_MDMA_ID U(5)
259#define STM32MP1_TZC_DMA_ID U(6)
260#define STM32MP1_TZC_USB_HOST_ID U(7)
261#define STM32MP1_TZC_USB_OTG_ID U(8)
262#define STM32MP1_TZC_SDMMC_ID U(9)
263#define STM32MP1_TZC_ETH_ID U(10)
264#define STM32MP1_TZC_DAP_ID U(15)
265
Yann Gautierf9d40d52019-01-17 14:41:46 +0100266#define STM32MP1_FILTER_BIT_ALL U(3)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200267
268/*******************************************************************************
269 * STM32MP1 SDMMC
270 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100271#define STM32MP_SDMMC1_BASE U(0x58005000)
272#define STM32MP_SDMMC2_BASE U(0x58007000)
273#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200274
Yann Gautier4baf5822019-05-09 13:25:52 +0200275#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
276#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
277#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
278#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
279#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200280
281/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100282 * STM32MP1 BSEC / OTP
283 ******************************************************************************/
284#define STM32MP1_OTP_MAX_ID 0x5FU
285#define STM32MP1_UPPER_OTP_START 0x20U
286
287#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
288
289/* OTP offsets */
290#define DATA0_OTP U(0)
Yann Gautierc7374052019-06-04 18:02:37 +0200291#define PART_NUMBER_OTP U(1)
Lionel Debieve402a46b2019-11-04 12:28:15 +0100292#define NAND_OTP U(9)
Yann Gautierc7374052019-06-04 18:02:37 +0200293#define PACKAGE_OTP U(16)
Yann Gautier3edc7c32019-05-20 19:17:08 +0200294#define HW2_OTP U(18)
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100295
296/* OTP mask */
297/* DATA0 */
298#define DATA0_OTP_SECURED BIT(6)
299
Yann Gautierc7374052019-06-04 18:02:37 +0200300/* PART NUMBER */
301#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
302#define PART_NUMBER_OTP_PART_SHIFT 0
303
304/* PACKAGE */
305#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
306#define PACKAGE_OTP_PKG_SHIFT 27
307
Yann Gautier091eab52019-06-04 18:06:34 +0200308/* IWDG OTP */
309#define HW2_OTP_IWDG_HW_POS U(3)
310#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
311#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
312
Yann Gautier3edc7c32019-05-20 19:17:08 +0200313/* HW2 OTP */
314#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
315
Lionel Debieve402a46b2019-11-04 12:28:15 +0100316/* NAND OTP */
317/* NAND parameter storage flag */
318#define NAND_PARAM_STORED_IN_OTP BIT(31)
319
320/* NAND page size in bytes */
321#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
322#define NAND_PAGE_SIZE_SHIFT 29
323#define NAND_PAGE_SIZE_2K U(0)
324#define NAND_PAGE_SIZE_4K U(1)
325#define NAND_PAGE_SIZE_8K U(2)
326
327/* NAND block size in pages */
328#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
329#define NAND_BLOCK_SIZE_SHIFT 27
330#define NAND_BLOCK_SIZE_64_PAGES U(0)
331#define NAND_BLOCK_SIZE_128_PAGES U(1)
332#define NAND_BLOCK_SIZE_256_PAGES U(2)
333
334/* NAND number of block (in unit of 256 blocs) */
335#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
336#define NAND_BLOCK_NB_SHIFT 19
337#define NAND_BLOCK_NB_UNIT U(256)
338
339/* NAND bus width in bits */
340#define NAND_WIDTH_MASK BIT(18)
341#define NAND_WIDTH_SHIFT 18
342
343/* NAND number of ECC bits per 512 bytes */
344#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
345#define NAND_ECC_BIT_NB_SHIFT 15
346#define NAND_ECC_BIT_NB_UNSET U(0)
347#define NAND_ECC_BIT_NB_1_BITS U(1)
348#define NAND_ECC_BIT_NB_4_BITS U(2)
349#define NAND_ECC_BIT_NB_8_BITS U(3)
350#define NAND_ECC_ON_DIE U(4)
351
Lionel Debieve186b0462019-09-24 18:30:12 +0200352/* NAND number of planes */
353#define NAND_PLANE_BIT_NB_MASK BIT(14)
354
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100355/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200356 * STM32MP1 TAMP
357 ******************************************************************************/
358#define TAMP_BASE U(0x5C00A000)
359#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
360
Julius Werner53456fc2019-07-09 13:49:11 -0700361#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Yann Gautier41934662018-07-20 11:36:05 +0200362static inline uint32_t tamp_bkpr(uint32_t idx)
363{
364 return TAMP_BKP_REGISTER_BASE + (idx << 2);
365}
366#endif
367
368/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200369 * STM32MP1 DDRCTRL
370 ******************************************************************************/
371#define DDRCTRL_BASE U(0x5A003000)
372
373/*******************************************************************************
374 * STM32MP1 DDRPHYC
375 ******************************************************************************/
376#define DDRPHYC_BASE U(0x5A004000)
377
378/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200379 * STM32MP1 IWDG
380 ******************************************************************************/
381#define IWDG_MAX_INSTANCE U(2)
382#define IWDG1_INST U(0)
383#define IWDG2_INST U(1)
384
385#define IWDG1_BASE U(0x5C003000)
386#define IWDG2_BASE U(0x5A002000)
387
388/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200389 * STM32MP1 I2C4
390 ******************************************************************************/
391#define I2C4_BASE U(0x5C002000)
392
Yann Gautier4d429472019-02-14 11:15:20 +0100393/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200394 * STM32MP1 DBGMCU
395 ******************************************************************************/
396#define DBGMCU_BASE U(0x50081000)
397
398/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100399 * Device Tree defines
400 ******************************************************************************/
Yann Gautier35dc0772019-05-13 18:34:48 +0200401#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Yann Gautier091eab52019-06-04 18:06:34 +0200402#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100403#define DT_PWR_COMPAT "st,stm32mp1-pwr"
Yann Gautier4d429472019-02-14 11:15:20 +0100404#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
Yann Gautier3edc7c32019-05-20 19:17:08 +0200405#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
Yann Gautier4d429472019-02-14 11:15:20 +0100406
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200407#endif /* STM32MP1_DEF_H */