Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <context_mgmt.h> |
| 36 | #include <debug.h> |
| 37 | #include <errno.h> |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 38 | #include <mce.h> |
Varun Wadekar | a7c1ea7 | 2016-02-03 09:51:25 -0800 | [diff] [blame] | 39 | #include <memctrl.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 40 | #include <runtime_svc.h> |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 41 | #include <t18x_ari.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 42 | #include <tegra_private.h> |
| 43 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 44 | extern uint32_t tegra186_system_powerdn_state; |
| 45 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 46 | /******************************************************************************* |
| 47 | * Tegra186 SiP SMCs |
| 48 | ******************************************************************************/ |
| 49 | #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 50 | #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01 |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 51 | #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00 |
| 52 | #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01 |
| 53 | #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02 |
| 54 | #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0x82FFFF03 |
| 55 | #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0x82FFFF04 |
| 56 | #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0x82FFFF05 |
| 57 | #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0x82FFFF06 |
| 58 | #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0x82FFFF07 |
| 59 | #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0x82FFFF08 |
| 60 | #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0x82FFFF09 |
| 61 | #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0x82FFFF0A |
| 62 | #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0x82FFFF0B |
| 63 | #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0x82FFFF0C |
| 64 | #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0x82FFFF0D |
| 65 | #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0x82FFFF0E |
| 66 | #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F |
Varun Wadekar | ad2824f | 2016-03-28 13:44:35 -0700 | [diff] [blame] | 67 | #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10 |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 68 | #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11 |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 69 | #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12 |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 70 | |
| 71 | /******************************************************************************* |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 72 | * This function is responsible for handling all T186 SiP calls |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 73 | ******************************************************************************/ |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 74 | int plat_sip_handler(uint32_t smc_fid, |
| 75 | uint64_t x1, |
| 76 | uint64_t x2, |
| 77 | uint64_t x3, |
| 78 | uint64_t x4, |
| 79 | void *cookie, |
| 80 | void *handle, |
| 81 | uint64_t flags) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 82 | { |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 83 | int mce_ret; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 84 | |
| 85 | switch (smc_fid) { |
| 86 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 87 | /* |
| 88 | * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - |
| 89 | * 0x82FFFFFF SiP SMC space |
| 90 | */ |
| 91 | case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: |
| 92 | case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: |
| 93 | case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: |
| 94 | case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: |
| 95 | case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: |
| 96 | case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: |
| 97 | case TEGRA_SIP_MCE_CMD_CC3_CTRL: |
| 98 | case TEGRA_SIP_MCE_CMD_ECHO_DATA: |
| 99 | case TEGRA_SIP_MCE_CMD_READ_VERSIONS: |
| 100 | case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: |
| 101 | case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: |
| 102 | case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: |
| 103 | case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: |
| 104 | case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: |
| 105 | case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: |
Varun Wadekar | ad2824f | 2016-03-28 13:44:35 -0700 | [diff] [blame] | 106 | case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 107 | case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 108 | case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 109 | |
| 110 | /* clean up the high bits */ |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 111 | smc_fid &= MCE_CMD_MASK; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 112 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 113 | /* execute the command and store the result */ |
| 114 | mce_ret = mce_command_handler(smc_fid, x1, x2, x3); |
| 115 | write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret); |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 116 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 117 | return 0; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 118 | |
Varun Wadekar | d66ee54 | 2016-02-29 10:24:30 -0800 | [diff] [blame] | 119 | case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: |
| 120 | |
| 121 | /* clean up the high bits */ |
| 122 | x1 = (uint32_t)x1; |
| 123 | |
| 124 | /* |
| 125 | * SC8 is a special Tegra186 system state where the CPUs and |
| 126 | * DRAM are powered down but the other subsystem is still |
| 127 | * alive. |
| 128 | */ |
| 129 | if ((x1 == TEGRA_ARI_SYSTEM_SC8) || |
| 130 | (x1 == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF)) { |
| 131 | |
| 132 | tegra186_system_powerdn_state = x1; |
| 133 | flush_dcache_range( |
| 134 | (uintptr_t)&tegra186_system_powerdn_state, |
| 135 | sizeof(tegra186_system_powerdn_state)); |
| 136 | |
| 137 | } else { |
| 138 | |
| 139 | ERROR("%s: unhandled powerdn state (%d)\n", __func__, |
| 140 | (uint32_t)x1); |
| 141 | return -ENOTSUP; |
| 142 | } |
| 143 | |
| 144 | return 0; |
| 145 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 146 | default: |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 147 | break; |
| 148 | } |
| 149 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 150 | return -ENOTSUP; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 151 | } |