blob: 496edf3cbe406408baf2ae90825239ac497d110f [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl_common.h>
35#include <context_mgmt.h>
36#include <debug.h>
37#include <errno.h>
38#include <memctrl.h>
39#include <runtime_svc.h>
40#include <tegra_private.h>
41
42/*******************************************************************************
43 * Tegra186 SiP SMCs
44 ******************************************************************************/
45#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
46
47/*******************************************************************************
48 * This function is responsible for handling all SiP calls from the NS world
49 ******************************************************************************/
50uint64_t tegra186_sip_handler(uint32_t smc_fid,
51 uint64_t x1,
52 uint64_t x2,
53 uint64_t x3,
54 uint64_t x4,
55 void *cookie,
56 void *handle,
57 uint64_t flags)
58{
59 uint32_t ns;
60 int err;
61
62 /* Determine which security state this SMC originated from */
63 ns = is_caller_non_secure(flags);
64 if (!ns)
65 SMC_RET1(handle, SMC_UNK);
66
67 switch (smc_fid) {
68
69 case TEGRA_SIP_NEW_VIDEOMEM_REGION:
70
71 /* clean up the high bits */
72 x1 = (uint32_t)x1;
73 x2 = (uint32_t)x2;
74
75 /*
76 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
77 * or falls outside of the valid DRAM range
78 */
79 err = bl31_check_ns_address(x1, x2);
80 if (err)
81 SMC_RET1(handle, err);
82
83 /*
84 * Check if Video Memory is aligned to 1MB.
85 */
86 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
87 ERROR("Unaligned Video Memory base address!\n");
88 SMC_RET1(handle, -ENOTSUP);
89 }
90
91 /* new video memory carveout settings */
92 tegra_memctrl_videomem_setup(x1, x2);
93
94 SMC_RET1(handle, 0);
95 break;
96
97 default:
98 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
99 break;
100 }
101
102 SMC_RET1(handle, SMC_UNK);
103}
104
105/* Define a runtime service descriptor for fast SMC calls */
106DECLARE_RT_SVC(
107 tegra186_sip_fast,
108
109 OEN_SIP_START,
110 OEN_SIP_END,
111 SMC_TYPE_FAST,
112 NULL,
113 tegra186_sip_handler
114);