blob: e11ead6087a59ed0f110fe787843f51e8d95f1c4 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Zelaleme8dadb12020-02-05 14:12:39 -06002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Dan Handleyed6ff952014-05-14 17:44:19 +01009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch.h>
Alexei Fedorovf41355c2019-09-13 14:11:59 +010012#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <arch_helpers.h>
14#include <bl1/bl1.h>
15#include <common/bl_common.h>
16#include <common/debug.h>
17#include <drivers/auth/auth_mod.h>
18#include <drivers/console.h>
19#include <lib/cpus/errata_report.h>
20#include <lib/utils.h>
21#include <plat/common/platform.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000022#include <smccc_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <tools_share/uuid.h>
24
Isla Mitchell99305012017-07-11 14:54:08 +010025#include "bl1_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010027/* BL1 Service UUID */
Roberto Vargaseace8f12018-04-26 13:36:53 +010028DEFINE_SVC_UUID2(bl1_svc_uid,
Zelaleme8dadb12020-02-05 14:12:39 -060029 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010030 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
31
Yatharth Kochara65be2f2015-10-09 18:06:13 +010032static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010033
Alexei Fedorov3dd9f2b2019-10-01 13:58:23 +010034#if ENABLE_PAUTH
35uint64_t bl1_apiakey[2];
36#endif
37
Sandrine Bailleux467d0572014-06-24 14:02:34 +010038/*******************************************************************************
Soby Mathew6e16a332018-01-10 12:51:34 +000039 * Helper utility to calculate the BL2 memory layout taking into consideration
40 * the BL1 RW data assuming that it is at the top of the memory layout.
Sandrine Bailleux467d0572014-06-24 14:02:34 +010041 ******************************************************************************/
Soby Mathew6e16a332018-01-10 12:51:34 +000042void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
43 meminfo_t *bl2_mem_layout)
Sandrine Bailleux467d0572014-06-24 14:02:34 +010044{
Sandrine Bailleux467d0572014-06-24 14:02:34 +010045 assert(bl1_mem_layout != NULL);
46 assert(bl2_mem_layout != NULL);
47
Yatharth Kochar51f76f62016-09-12 16:10:33 +010048 /*
49 * Remove BL1 RW data from the scope of memory visible to BL2.
50 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
51 */
52 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
53 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
54 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
Sandrine Bailleux467d0572014-06-24 14:02:34 +010055
Deepika Bhavnani64e557c2019-09-03 21:51:09 +030056 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
Sandrine Bailleux467d0572014-06-24 14:02:34 +010057}
Soby Mathew6e16a332018-01-10 12:51:34 +000058
Sandrine Bailleux467d0572014-06-24 14:02:34 +010059/*******************************************************************************
Antonio Nino Diaze3887a92019-01-30 20:29:50 +000060 * Setup function for BL1.
61 ******************************************************************************/
62void bl1_setup(void)
63{
64 /* Perform early platform-specific setup */
65 bl1_early_platform_setup();
66
Antonio Nino Diaze3887a92019-01-30 20:29:50 +000067 /* Perform late platform-specific setup */
68 bl1_plat_arch_setup();
Alexei Fedorovf41355c2019-09-13 14:11:59 +010069
70#if CTX_INCLUDE_PAUTH_REGS
71 /*
72 * Assert that the ARMv8.3-PAuth registers are present or an access
73 * fault will be triggered when they are being saved or restored.
74 */
75 assert(is_armv8_3_pauth_present());
76#endif /* CTX_INCLUDE_PAUTH_REGS */
Antonio Nino Diaze3887a92019-01-30 20:29:50 +000077}
78
79/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010080 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +010081 * It also queries the platform to load and run next BL image. Only called
82 * by the primary cpu after a cold boot.
83 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +010084void bl1_main(void)
85{
Yatharth Kochara65be2f2015-10-09 18:06:13 +010086 unsigned int image_id;
87
Dan Handley91b624e2014-07-29 17:14:00 +010088 /* Announce our arrival */
89 NOTICE(FIRMWARE_WELCOME_STR);
90 NOTICE("BL1: %s\n", version_string);
91 NOTICE("BL1: %s\n", build_message);
92
Yatharth Kochar5d361212016-06-28 17:07:09 +010093 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
94 (void *)BL1_RAM_LIMIT);
Dan Handley91b624e2014-07-29 17:14:00 +010095
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000096 print_errata_status();
Achin Gupta4f6ad662013-10-25 09:08:21 +010097
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +000098#if ENABLE_ASSERTIONS
Yatharth Kochar5d361212016-06-28 17:07:09 +010099 u_register_t val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100 /*
101 * Ensure that MMU/Caches and coherency are turned on
102 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700103#ifdef __aarch64__
Dan Handley0cdebbd2015-03-30 17:15:16 +0100104 val = read_sctlr_el3();
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700105#else
106 val = read_sctlr();
Yatharth Kochar5d361212016-06-28 17:07:09 +0100107#endif
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100108 assert(val & SCTLR_M_BIT);
109 assert(val & SCTLR_C_BIT);
110 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100111 /*
112 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
113 * provided platform value
114 */
115 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
116 /*
117 * If CWG is zero, then no CWG information is available but we can
118 * at least check the platform value is less than the architectural
119 * maximum.
120 */
121 if (val != 0)
122 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
123 else
124 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +0000125#endif /* ENABLE_ASSERTIONS */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126
127 /* Perform remaining generic architectural setup from EL3 */
128 bl1_arch_setup();
129
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100130#if TRUSTED_BOARD_BOOT
131 /* Initialize authentication module */
132 auth_mod_init();
133#endif /* TRUSTED_BOARD_BOOT */
134
Achin Gupta4f6ad662013-10-25 09:08:21 +0100135 /* Perform platform setup in BL1. */
136 bl1_platform_setup();
137
Alexei Fedorov3dd9f2b2019-10-01 13:58:23 +0100138#if ENABLE_PAUTH
139 /* Store APIAKey_EL1 key */
140 bl1_apiakey[0] = read_apiakeylo_el1();
141 bl1_apiakey[1] = read_apiakeyhi_el1();
142#endif /* ENABLE_PAUTH */
143
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100144 /* Get the image id of next image to load and run. */
145 image_id = bl1_plat_get_next_image_id();
146
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100147 /*
148 * We currently interpret any image id other than
149 * BL2_IMAGE_ID as the start of firmware update.
150 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100151 if (image_id == BL2_IMAGE_ID)
152 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100153 else
154 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100155
156 bl1_prepare_next_image(image_id);
Antonio Nino Diaze3962d02017-02-16 16:17:19 +0000157
158 console_flush();
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100159}
160
161/*******************************************************************************
162 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
163 * Called by the primary cpu after a cold boot.
164 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
165 * loader etc.
166 ******************************************************************************/
Roberto Vargasbcfaeff2018-02-12 12:36:17 +0000167static void bl1_load_bl2(void)
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100168{
169 image_desc_t *image_desc;
170 image_info_t *image_info;
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100171 int err;
172
173 /* Get the image descriptor */
174 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
Zelaleme8dadb12020-02-05 14:12:39 -0600175 assert(image_desc != NULL);
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100176
177 /* Get the image info */
178 image_info = &image_desc->image_info;
Juan Castillo3a66aca2015-04-13 17:36:19 +0100179 INFO("BL1: Loading BL2\n");
180
Soby Mathew2f38ce32018-02-08 17:45:12 +0000181 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900182 if (err) {
183 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
184 plat_error_handler(err);
185 }
186
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100187 err = load_auth_image(BL2_IMAGE_ID, image_info);
Vikram Kanigirida567432014-04-15 18:08:08 +0100188 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100189 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100190 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100191 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000192
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900193 /* Allow platform to handle image information. */
Soby Mathew2f38ce32018-02-08 17:45:12 +0000194 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
Masahiro Yamada43d20b32018-02-01 16:46:18 +0900195 if (err) {
196 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
197 plat_error_handler(err);
198 }
199
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100200 NOTICE("BL1: Booting BL2\n");
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201}
202
203/*******************************************************************************
Yatharth Kochar5d361212016-06-28 17:07:09 +0100204 * Function called just before handing over to the next BL to inform the user
205 * about the boot progress. In debug mode, also print details about the BL
206 * image's execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207 ******************************************************************************/
Yatharth Kochar5d361212016-06-28 17:07:09 +0100208void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209{
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700210#ifdef __aarch64__
Juan Castillo7d199412015-12-14 09:35:25 +0000211 NOTICE("BL1: Booting BL31\n");
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700212#else
213 NOTICE("BL1: Booting BL32\n");
214#endif /* __aarch64__ */
Yatharth Kochar5d361212016-06-28 17:07:09 +0100215 print_entry_point_info(bl_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000217
218#if SPIN_ON_BL1_EXIT
219void print_debug_loop_message(void)
220{
221 NOTICE("BL1: Debug loop, spinning forever\n");
222 NOTICE("BL1: Please connect the debugger to continue\n");
223}
224#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100225
226/*******************************************************************************
227 * Top level handler for servicing BL1 SMCs.
228 ******************************************************************************/
Zelalem91d80612020-02-12 10:37:03 -0600229u_register_t bl1_smc_handler(unsigned int smc_fid,
230 u_register_t x1,
231 u_register_t x2,
232 u_register_t x3,
233 u_register_t x4,
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100234 void *cookie,
235 void *handle,
236 unsigned int flags)
237{
238
239#if TRUSTED_BOARD_BOOT
240 /*
241 * Dispatch FWU calls to FWU SMC handler and return its return
242 * value
243 */
244 if (is_fwu_fid(smc_fid)) {
245 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
246 handle, flags);
247 }
248#endif
249
250 switch (smc_fid) {
251 case BL1_SMC_CALL_COUNT:
252 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
253
254 case BL1_SMC_UID:
255 SMC_UUID_RET(handle, bl1_svc_uid);
256
257 case BL1_SMC_VERSION:
258 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
259
260 default:
261 break;
262 }
263
264 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
265 SMC_RET1(handle, SMC_UNK);
266}
dp-armcdd03cb2017-02-15 11:07:55 +0000267
268/*******************************************************************************
269 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
270 * compliance when invoking bl1_smc_handler.
271 ******************************************************************************/
Zelalem91d80612020-02-12 10:37:03 -0600272u_register_t bl1_smc_wrapper(uint32_t smc_fid,
dp-armcdd03cb2017-02-15 11:07:55 +0000273 void *cookie,
274 void *handle,
275 unsigned int flags)
276{
Zelalem91d80612020-02-12 10:37:03 -0600277 u_register_t x1, x2, x3, x4;
dp-armcdd03cb2017-02-15 11:07:55 +0000278
Zelaleme8dadb12020-02-05 14:12:39 -0600279 assert(handle != NULL);
dp-armcdd03cb2017-02-15 11:07:55 +0000280
281 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
282 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
283}