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git01.mediatek.com / filogic / atf / cc5f89a792c51d4836805046db628eb3ff80fc26 / . / plat / arm / css / sgm / sgm-common.mk
blob: 5b954f8423b900b400b876589c2f123ad3e26d20 [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]1#
Alexei Fedorov2f13d6c2020-02-21 10:17:26 +0000[diff] [blame]2# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chris Kayf9c4cf42019-04-23 16:31:06 +0100[diff] [blame]7CSS_USE_SCMI_SDS_DRIVER := 1
8
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]9CSS_SGM_BASE := plat/arm/css/sgm
10
11PLAT_INCLUDES := -I${CSS_SGM_BASE}/include
12
13PLAT_BL_COMMON_SOURCES := ${CSS_SGM_BASE}/sgm_mmap_config.c \
14 ${CSS_SGM_BASE}/aarch64/css_sgm_helpers.S
15
16SECURITY_SOURCES := drivers/arm/tzc/tzc_dmc500.c \
Ambroise Vincent322971d2019-04-11 13:45:18 +0100[diff] [blame]17 plat/arm/common/arm_tzc_dmc500.c \
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]18 ${CSS_SGM_BASE}/sgm_security.c
19
20SGM_CPU_SOURCES := lib/cpus/aarch64/cortex_a55.S \
21 lib/cpus/aarch64/cortex_a75.S
22
23INTERCONNECT_SOURCES := ${CSS_SGM_BASE}/sgm_interconnect.c
24
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]25# GIC-600 configuration
Andre Przywarae1cc1302020-03-25 15:50:38 +0000[diff] [blame]26GICV3_SUPPORT_GIC600 := 1
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]27
28# Include GICv3 driver files
29include drivers/arm/gic/v3/gicv3.mk
30
31SGM_GIC_SOURCES := ${GICV3_SOURCES} \
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]32 plat/common/plat_gicv3.c \
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]33 plat/arm/common/arm_gicv3.c
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]34
35BL1_SOURCES += $(SGM_CPU_SOURCES) \
36 ${INTERCONNECT_SOURCES} \
Ambroise Vincent322971d2019-04-11 13:45:18 +0100[diff] [blame]37 ${CSS_SGM_BASE}/sgm_bl1_setup.c \
Aditya Angadi20b48412019-04-16 11:29:14 +0530[diff] [blame]38 ${CSS_SGM_BASE}/sgm_plat_config.c \
39 drivers/arm/sp805/sp805.c
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]40
Ambroise Vincent322971d2019-04-11 13:45:18 +0100[diff] [blame]41BL2_SOURCES += ${SECURITY_SOURCES} \
42 ${CSS_SGM_BASE}/sgm_plat_config.c
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]43
44BL2U_SOURCES += ${SECURITY_SOURCES}
45
46BL31_SOURCES += $(SGM_CPU_SOURCES) \
47 ${INTERCONNECT_SOURCES} \
48 ${SECURITY_SOURCES} \
49 ${SGM_GIC_SOURCES} \
Ambroise Vincent322971d2019-04-11 13:45:18 +0100[diff] [blame]50 ${CSS_SGM_BASE}/sgm_topology.c \
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]51 ${CSS_SGM_BASE}/sgm_bl31_setup.c \
52 ${CSS_SGM_BASE}/sgm_plat_config.c
53
Deepak Pandeyb0971f92018-05-25 12:43:30 +0530[diff] [blame]54ifneq (${RESET_TO_BL31},0)
Sandrine Bailleux1e32d322019-01-07 15:35:37 +0100[diff] [blame]55 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Deepak Pandeyb0971f92018-05-25 12:43:30 +0530[diff] [blame]56 Please set RESET_TO_BL31 to 0.")
57endif
58
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]59# sgm uses CCI-500 as Cache Coherent Interconnect
60ARM_CCI_PRODUCT_ID := 500
61
Nariman Poushinc703f902018-03-07 10:29:57 +0000[diff] [blame]62# System coherency is managed in hardware
63HW_ASSISTED_COHERENCY := 1
64
65# When building for systems with hardware-assisted coherency, there's no need to
66# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
67USE_COHERENT_MEM := 0
68
69override ARM_PLAT_MT := 1
70
71$(eval $(call add_define,SGM_PLAT))
72
73include plat/arm/common/arm_common.mk
74include plat/arm/board/common/board_common.mk
75include plat/arm/css/common/css_common.mk
76include plat/arm/soc/common/soc_css.mk