blob: cb5a55352e4430793cd678954305e0b51eae648e [file] [log] [blame]
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +02001#
Madhukar Pappireddycc307102023-09-09 23:02:34 -05002# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +02003#
4# Copyright (c) 2017-2023 Nuvoton Ltd.
5#
6# SPDX-License-Identifier: BSD-3-Clause
7#
8
9# This is a debug flag for bring-up. It allows reducing CPU numbers
10# SECONDARY_BRINGUP := 1
11RESET_TO_BL31 := 1
Margarita Glushkinf52f6ae2023-08-15 16:44:07 +030012SPMD_SPM_AT_SEL2 := 0
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +020013#temporary until the RAM size is reduced
14USE_COHERENT_MEM := 1
15
16
17$(eval $(call add_define,RESET_TO_BL31))
18
19ifeq (${ARCH}, aarch64)
20# On ARM standard platorms, the TSP can execute from Trusted SRAM,
21# Trusted DRAM (if available) or the TZC secured area of DRAM.
22# TZC secured DRAM is the default.
23
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +020024# Process ARM_BL31_IN_DRAM flag
25ARM_BL31_IN_DRAM := 0
26$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
27$(eval $(call add_define,ARM_BL31_IN_DRAM))
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +020028endif
29
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +020030# For the original power-state parameter format, the State-ID can be encoded
31# according to the recommended encoding or zero. This flag determines which
32# State-ID encoding to be parsed.
33ARM_RECOM_STATE_ID_ENC := 0
34
35# If the PSCI_EXTENDED_STATE_ID is set, then ARM_RECOM_STATE_ID_ENC
36# need to be set. Else throw a build error.
37ifeq (${PSCI_EXTENDED_STATE_ID}, 1)
38ifeq (${ARM_RECOM_STATE_ID_ENC}, 0)
39$(error Build option ARM_RECOM_STATE_ID_ENC needs to be set if \
40 PSCI_EXTENDED_STATE_ID is set for ARM platforms)
41endif
42endif
43
44# Process ARM_RECOM_STATE_ID_ENC flag
45$(eval $(call assert_boolean,ARM_RECOM_STATE_ID_ENC))
46$(eval $(call add_define,ARM_RECOM_STATE_ID_ENC))
47
48# Process ARM_DISABLE_TRUSTED_WDOG flag
49# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set
50ARM_DISABLE_TRUSTED_WDOG := 0
51ifeq (${SPIN_ON_BL1_EXIT}, 1)
52ARM_DISABLE_TRUSTED_WDOG := 1
53endif
54$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG))
55$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG))
56
57# Process ARM_CONFIG_CNTACR
58ARM_CONFIG_CNTACR := 1
59$(eval $(call assert_boolean,ARM_CONFIG_CNTACR))
60$(eval $(call add_define,ARM_CONFIG_CNTACR))
61
62# Process ARM_BL31_IN_DRAM flag
63ARM_BL31_IN_DRAM := 0
64$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
65$(eval $(call add_define,ARM_BL31_IN_DRAM))
66
67# Process ARM_PLAT_MT flag
68ARM_PLAT_MT := 0
69$(eval $(call assert_boolean,ARM_PLAT_MT))
70$(eval $(call add_define,ARM_PLAT_MT))
71
72# Use translation tables library v2 by default
73ARM_XLAT_TABLES_LIB_V1 := 0
74$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
75$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
76
77# Don't have the Linux kernel as a BL33 image by default
78ARM_LINUX_KERNEL_AS_BL33 := 0
79$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
80$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
81
82ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
83ifeq (${ARCH},aarch64)
84ifneq (${RESET_TO_BL31},1)
85$(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_BL31=1.")
86endif
87else
88ifneq (${RESET_TO_SP_MIN},1)
89$(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.")
90endif
91endif
92
93ifndef PRELOADED_BL33_BASE
94$(error "PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
95endif
96
97ifndef ARM_PRELOADED_DTB_BASE
98$(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
99endif
100
101$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
102endif
103
104# Use an implementation of SHA-256 with a smaller memory footprint
105# but reduced speed.
106$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
107
108# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
109# in the FIP if the platform requires.
110ifneq ($(BL32_EXTRA1),)
111$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
112endif
113ifneq ($(BL32_EXTRA2),)
114$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
115endif
116
117# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms
118ENABLE_PSCI_STAT := 1
119ENABLE_PMF := 1
120
121# On ARM platforms, separate the code and read-only data sections to allow
122# mapping the former as executable and the latter as execute-never.
123SEPARATE_CODE_AND_RODATA := 1
124
125# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS
126# and NOBITS sections of BL31 image are adjacent to each other and loaded
127# into Trusted SRAM.
128SEPARATE_NOBITS_REGION := 0
129
130# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
131# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
132# the build to require that ARM_BL31_IN_DRAM is enabled as well.
133ifeq ($(SEPARATE_NOBITS_REGION),1)
134ifneq ($(ARM_BL31_IN_DRAM),1)
135$(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled)
136endif
137
138ifneq ($(RECLAIM_INIT_CODE),0)
139$(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported)
140endif
141endif
142
143# Disable ARM Cryptocell by default
144ARM_CRYPTOCELL_INTEG := 0
145$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
146$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
147
148# Enable PIE support for RESET_TO_BL31 case
149ifeq (${RESET_TO_BL31},1)
150ENABLE_PIE := 1
151endif
152
153# CryptoCell integration relies on coherent buffers for passing data from
154# the AP CPU to the CryptoCell
155
156ifeq (${ARM_CRYPTOCELL_INTEG},1)
157ifeq (${USE_COHERENT_MEM},0)
158$(error "ARM_CRYPTOCELL_INTEG needs USE_COHERENT_MEM to be set.")
159endif
160endif
161
162PLAT_INCLUDES := -Iinclude/plat/nuvoton/npcm845x \
163 -Iinclude/plat/nuvoton/common \
164 -Iinclude/drivers/nuvoton/npcm845x \
165
166ifeq (${ARCH}, aarch64)
167PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
168endif
169
170# Include GICv3 driver files
171include drivers/arm/gic/v2/gicv2.mk
172
173NPCM850_GIC_SOURCES := ${GICV2_SOURCES}
174
175BL31_SOURCES +=lib/cpus/aarch64/cortex_a35.S \
176 plat/common/plat_psci_common.c \
177 drivers/ti/uart/aarch64/16550_console.S \
178 plat/nuvoton/npcm845x/npcm845x_psci.c \
179 plat/nuvoton/npcm845x/npcm845x_serial_port.c \
180 plat/nuvoton/common/nuvoton_topology.c \
181 plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
182
183PLAT_BL_COMMON_SOURCES := drivers/delay_timer/delay_timer.c \
184 drivers/delay_timer/generic_delay_timer.c \
185 plat/common/plat_gicv2.c \
186 plat/arm/common/arm_gicv2.c \
187 plat/nuvoton/common/plat_nuvoton_gic.c \
188 ${NPCM850_GIC_SOURCES} \
189 plat/nuvoton/npcm845x/npcm845x_common.c \
190 plat/nuvoton/common/nuvoton_helpers.S \
191 lib/semihosting/semihosting.c \
192 lib/semihosting/${ARCH}/semihosting_call.S \
193 plat/arm/common/arm_common.c \
194 plat/arm/common/arm_console.c
195
196ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
197PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
198 lib/xlat_tables/${ARCH}/xlat_tables.c
199else
200include lib/xlat_tables_v2/xlat_tables.mk
201
202PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
203endif
204
205ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c \
206 plat/arm/common/fconf/arm_fconf_io.c
207
208ifeq (${SPD},spmd)
209ifeq (${SPMD_SPM_AT_SEL2},1)
210ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c
211endif
212endif
213
214BL1_SOURCES += drivers/io/io_fip.c \
215 drivers/io/io_memmap.c \
216 drivers/io/io_storage.c \
217 plat/arm/common/arm_bl1_setup.c \
218 plat/arm/common/arm_err.c \
219 ${ARM_IO_SOURCES}
220
221ifdef EL3_PAYLOAD_BASE
222# Need the plat_arm_program_trusted_mailbox() function to release secondary CPUs
223# from their holding pen
224BL1_SOURCES += plat/arm/common/arm_pm.c
225endif
226
227BL2_SOURCES += drivers/delay_timer/delay_timer.c \
228 drivers/delay_timer/generic_delay_timer.c \
229 drivers/io/io_fip.c \
230 drivers/io/io_memmap.c \
231 drivers/io/io_storage.c \
232 plat/arm/common/arm_bl2_setup.c \
233 plat/arm/common/arm_err.c \
234 ${ARM_IO_SOURCES}
235
236# Firmware Configuration Framework sources
237include lib/fconf/fconf.mk
238
239# Add `libfdt` and Arm common helpers required for Dynamic Config
240include lib/libfdt/libfdt.mk
241
242DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
243 plat/arm/common/arm_dyn_cfg_helpers.c \
244 common/fdt_wrappers.c
245
246BL1_SOURCES += ${DYN_CFG_SOURCES}
247BL2_SOURCES += ${DYN_CFG_SOURCES}
248
249ifeq (${BL2_AT_EL3},1)
250BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c
251endif
252
253# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
254# the AArch32 descriptors.
255BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
256BL2_SOURCES += plat/arm/common/arm_image_load.c \
257 common/desc_image_load.c
258
259ifeq (${SPD},opteed)
260BL2_SOURCES += lib/optee/optee_utils.c
261endif
262
263BL2U_SOURCES += drivers/delay_timer/delay_timer.c \
264 drivers/delay_timer/generic_delay_timer.c \
265 plat/arm/common/arm_bl2u_setup.c
266
267BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \
268 plat/nuvoton/common/nuvoton_pm.c \
269 plat/nuvoton/common/nuvoton_topology.c \
270 plat/common/plat_psci_common.c
271
272ifeq (${ENABLE_PMF}, 1)
273ifeq (${ARCH}, aarch64)
274BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c \
275 plat/arm/common/arm_sip_svc.c \
Madhukar Pappireddycc307102023-09-09 23:02:34 -0500276 plat/arm/common/plat_arm_sip_svc.c \
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +0200277 lib/pmf/pmf_smc.c
278else
279BL32_SOURCES += plat/arm/common/arm_sip_svc.c \
Madhukar Pappireddycc307102023-09-09 23:02:34 -0500280 plat/arm/common/plat_arm_sip_svc.c \
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +0200281 lib/pmf/pmf_smc.c
282endif
283endif
284
285ifeq (${EL3_EXCEPTION_HANDLING},1)
286BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c
287endif
288
289ifeq (${SDEI_SUPPORT},1)
290BL31_SOURCES += plat/arm/common/aarch64/arm_sdei.c
291ifeq (${SDEI_IN_FCONF},1)
292BL31_SOURCES += plat/arm/common/fconf/fconf_sdei_getter.c
293endif
294endif
295
296# RAS sources
297ifeq (${RAS_EXTENSION},1)
298BL31_SOURCES += lib/extensions/ras/std_err_record.c \
299 lib/extensions/ras/ras_common.c
300endif
301
302# Pointer Authentication sources
303ifeq (${ENABLE_PAUTH}, 1)
Govindraj Raja53020692023-08-21 16:32:20 -0500304PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +0200305endif
306
307ifeq (${SPD},spmd)
308BL31_SOURCES += plat/common/plat_spmd_manifest.c \
309 common/fdt_wrappers.c \
310 ${LIBFDT_SRCS}
311endif
312
313ifneq (${TRUSTED_BOARD_BOOT},0)
314# Include common TBB sources
315AUTH_SOURCES := drivers/auth/auth_mod.c \
316 drivers/auth/crypto_mod.c \
317 drivers/auth/img_parser_mod.c \
318 lib/fconf/fconf_tbbr_getter.c
319
320# Include the selected chain of trust sources.
321ifeq (${COT},tbbr)
322AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
323BL1_SOURCES += drivers/auth/tbbr/tbbr_cot_bl1.c
324BL2_SOURCES += drivers/auth/tbbr/tbbr_cot_bl2.c
325else ifeq (${COT},dualroot)
326AUTH_SOURCES += drivers/auth/dualroot/cot.c
327else
328$(error Unknown chain of trust ${COT})
329endif
330
331BL1_SOURCES += ${AUTH_SOURCES} \
332 bl1/tbbr/tbbr_img_desc.c \
333 plat/arm/common/arm_bl1_fwu.c \
334 plat/common/tbbr/plat_tbbr.c
335
336BL2_SOURCES += ${AUTH_SOURCES} \
337 plat/common/tbbr/plat_tbbr.c
338
339$(eval $(call TOOL_ADD_IMG,ns_bl2u,--fwu,FWU_))
340
341# We expect to locate the *.mk files under the directories specified below
342ifeq (${ARM_CRYPTOCELL_INTEG},0)
343CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
344else
345CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk
346endif
347
348IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk
349
350$(info Including ${CRYPTO_LIB_MK})
351include ${CRYPTO_LIB_MK}
352
353$(info Including ${IMG_PARSER_LIB_MK})
354include ${IMG_PARSER_LIB_MK}
355endif
356
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +0200357ifeq (${MEASURED_BOOT},1)
358MEASURED_BOOT_MK := drivers/measured_boot/measured_boot.mk
359$(info Including ${MEASURED_BOOT_MK})
360include ${MEASURED_BOOT_MK}
361endif
362
363ifeq (${EL3_EXCEPTION_HANDLING},1)
364BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c
365endif
366
367BL1_SOURCES :=
368BL2_SOURCES :=
369BL2U_SOURCES :=
370
371DEBUG_CONSOLE ?= 0
372$(eval $(call add_define,DEBUG_CONSOLE))