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git01.mediatek.com / filogic / atf / cbad66172122a5d5d3c15a345ed6e592d4e24fce / . / plat / arm / css / sgi / aarch64 / sgi_helper.S
blob: dd0fc5bbd26819b4dc626afd3d7f628f3bd3bdec [file] [log] [blame]
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]1/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
Chandni Cherukuri82718852018-08-02 12:29:07 +0530[diff] [blame]10#include <cortex_a75.h>
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]11
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]12 .globl plat_arm_calc_core_pos
Chandni Cherukuri82718852018-08-02 12:29:07 +0530[diff] [blame]13 .globl plat_reset_handler
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]14
15 /* -----------------------------------------------------
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +0530[diff] [blame]16 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
17 *
18 * Helper function to calculate the core position.
19 * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
20 * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
21 * ThreadId
22 *
23 * which can be simplified as:
24 *
25 * ((ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER + CPUId) *
26 * CSS_SGI_MAX_PE_PER_CPU) + ThreadId
27 * ------------------------------------------------------
28 */
29
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]30func plat_arm_calc_core_pos
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +0530[diff] [blame]31 mov x3, x0
32
33 /*
34 * The MT bit in MPIDR is always set for SGI platforms
35 * and the affinity level 0 corresponds to thread affinity level.
36 */
37
38 /* Extract individual affinity fields from MPIDR */
39 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
40 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
42
43 /* Compute linear position */
44 mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
45 madd x1, x2, x4, x1
46 mov x5, #CSS_SGI_MAX_PE_PER_CPU
47 madd x0, x1, x5, x0
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]48 ret
49endfunc plat_arm_calc_core_pos
Chandni Cherukuri82718852018-08-02 12:29:07 +0530[diff] [blame]50
51 /* ------------------------------------------------------
52 * Helper macro that reads the part number of the current
53 * CPU and jumps to the given label if it matches the CPU
54 * MIDR provided.
55 *
56 * Clobbers x0.
57 * -----------------------------------------------------
58 */
59 .macro jump_if_cpu_midr _cpu_midr, _label
60 mrs x0, midr_el1
61 ubfx x0, x0, MIDR_PN_SHIFT, #12
62 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
63 b.eq \_label
64 .endm
65
66 /* -----------------------------------------------------
67 * void plat_reset_handler(void);
68 *
69 * Determine the CPU MIDR and disable power down bit for
70 * that CPU.
71 * -----------------------------------------------------
72 */
73func plat_reset_handler
74 jump_if_cpu_midr CORTEX_A75_MIDR, A75
75 ret
76
77 /* -----------------------------------------------------
78 * Disable CPU power down bit in power control register
79 * -----------------------------------------------------
80 */
81A75:
82 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
83 bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
84 msr CORTEX_A75_CPUPWRCTLR_EL1, x0
85 isb
86 ret
87endfunc plat_reset_handler