Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_A57_H__ |
| 8 | #define __CORTEX_A57_H__ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 9 | #include <utils_def.h> |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 10 | |
| 11 | /* Cortex-A57 midr for revision 0 */ |
| 12 | #define CORTEX_A57_MIDR 0x410FD070 |
| 13 | |
| 14 | /* Retention timer tick definitions */ |
| 15 | #define RETENTION_ENTRY_TICKS_2 0x1 |
| 16 | #define RETENTION_ENTRY_TICKS_8 0x2 |
| 17 | #define RETENTION_ENTRY_TICKS_32 0x3 |
| 18 | #define RETENTION_ENTRY_TICKS_64 0x4 |
| 19 | #define RETENTION_ENTRY_TICKS_128 0x5 |
| 20 | #define RETENTION_ENTRY_TICKS_256 0x6 |
| 21 | #define RETENTION_ENTRY_TICKS_512 0x7 |
| 22 | |
| 23 | /******************************************************************************* |
| 24 | * CPU Extended Control register specific definitions. |
| 25 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 26 | #define CORTEX_A57_ECTLR p15, 1, c15 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 27 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 28 | #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6) |
| 29 | #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) |
| 30 | #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) |
| 31 | #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 32 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 33 | #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 34 | #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 35 | |
| 36 | /******************************************************************************* |
| 37 | * CPU Memory Error Syndrome register specific definitions. |
| 38 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 39 | #define CORTEX_A57_CPUMERRSR p15, 2, c15 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
| 42 | * CPU Auxiliary Control register specific definitions. |
| 43 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 44 | #define CORTEX_A57_CPUACTLR p15, 0, c15 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 45 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 46 | #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) |
Dimitris Papastamos | 4a284a4 | 2018-05-17 14:41:13 +0100 | [diff] [blame] | 47 | #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 48 | #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) |
| 49 | #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52) |
| 50 | #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) |
| 51 | #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) |
| 52 | #define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 53 | #define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 54 | #define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27) |
| 55 | #define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25) |
| 56 | #define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 57 | |
| 58 | /******************************************************************************* |
| 59 | * L2 Control register specific definitions. |
| 60 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 61 | #define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 62 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 63 | #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 |
| 64 | #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 65 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 66 | #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 |
| 67 | #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 68 | |
| 69 | /******************************************************************************* |
| 70 | * L2 Extended Control register specific definitions. |
| 71 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 72 | #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 73 | |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 74 | #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 75 | #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 76 | |
| 77 | /******************************************************************************* |
| 78 | * L2 Memory Error Syndrome register specific definitions. |
| 79 | ******************************************************************************/ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 80 | #define CORTEX_A57_L2MERRSR p15, 3, c15 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 81 | |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 82 | #endif /* __CORTEX_A57_H__ */ |