| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame^] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_A57_H__ |
| 8 | #define __CORTEX_A57_H__ |
| 9 | |
| 10 | /* Cortex-A57 midr for revision 0 */ |
| 11 | #define CORTEX_A57_MIDR 0x410FD070 |
| 12 | |
| 13 | /* Retention timer tick definitions */ |
| 14 | #define RETENTION_ENTRY_TICKS_2 0x1 |
| 15 | #define RETENTION_ENTRY_TICKS_8 0x2 |
| 16 | #define RETENTION_ENTRY_TICKS_32 0x3 |
| 17 | #define RETENTION_ENTRY_TICKS_64 0x4 |
| 18 | #define RETENTION_ENTRY_TICKS_128 0x5 |
| 19 | #define RETENTION_ENTRY_TICKS_256 0x6 |
| 20 | #define RETENTION_ENTRY_TICKS_512 0x7 |
| 21 | |
| 22 | /******************************************************************************* |
| 23 | * CPU Extended Control register specific definitions. |
| 24 | ******************************************************************************/ |
| 25 | #define CPUECTLR p15, 1, c15 /* Instruction def. */ |
| 26 | |
| 27 | #define CPUECTLR_SMP_BIT (1 << 6) |
| 28 | #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) |
| 29 | #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) |
| 30 | #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) |
| 31 | |
| 32 | #define CPUECTLR_CPU_RET_CTRL_SHIFT 0 |
| 33 | #define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) |
| 34 | |
| 35 | /******************************************************************************* |
| 36 | * CPU Memory Error Syndrome register specific definitions. |
| 37 | ******************************************************************************/ |
| 38 | #define CPUMERRSR p15, 2, c15 /* Instruction def. */ |
| 39 | |
| 40 | /******************************************************************************* |
| 41 | * CPU Auxiliary Control register specific definitions. |
| 42 | ******************************************************************************/ |
| 43 | #define CPUACTLR p15, 0, c15 /* Instruction def. */ |
| 44 | |
| 45 | #define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) |
| 46 | #define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) |
| 47 | #define CPUACTLR_DIS_OVERREAD (1 << 52) |
| 48 | #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) |
| 49 | #define CPUACTLR_DCC_AS_DCCI (1 << 44) |
| 50 | #define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38) |
| 51 | #define CPUACTLR_DIS_STREAMING (3 << 27) |
| 52 | #define CPUACTLR_DIS_L1_STREAMING (3 << 25) |
| 53 | #define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) |
| 54 | |
| 55 | /******************************************************************************* |
| 56 | * L2 Control register specific definitions. |
| 57 | ******************************************************************************/ |
| 58 | #define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */ |
| 59 | |
| 60 | #define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 |
| 61 | #define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 |
| 62 | |
| 63 | #define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 |
| 64 | #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 |
| 65 | |
| 66 | /******************************************************************************* |
| 67 | * L2 Extended Control register specific definitions. |
| 68 | ******************************************************************************/ |
| 69 | #define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */ |
| 70 | |
| 71 | #define L2ECTLR_RET_CTRL_SHIFT 0 |
| 72 | #define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) |
| 73 | |
| 74 | /******************************************************************************* |
| 75 | * L2 Memory Error Syndrome register specific definitions. |
| 76 | ******************************************************************************/ |
| 77 | #define L2MERRSR p15, 3, c15 /* Instruction def. */ |
| 78 | |
| 79 | #endif /* __CORTEX_A57_H__ */ |