Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_FCS_H |
| 8 | #define SOCFPGA_FCS_H |
| 9 | |
| 10 | /* FCS Definitions */ |
| 11 | |
| 12 | #define FCS_RANDOM_WORD_SIZE 8U |
| 13 | #define FCS_PROV_DATA_WORD_SIZE 44U |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 14 | #define FCS_SHA384_WORD_SIZE 12U |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 15 | |
| 16 | #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) |
| 17 | #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 18 | #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 19 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 20 | #define FCS_MODE_DECRYPT 0x0 |
| 21 | #define FCS_MODE_ENCRYPT 0x1 |
| 22 | #define FCS_ENCRYPTION_DATA_0 0x10100 |
| 23 | #define FCS_DECRYPTION_DATA_0 0x10102 |
| 24 | #define FCS_OWNER_ID_OFFSET 0xC |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 25 | |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 26 | #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 |
| 27 | #define PSGSIGMA_SESSION_ID_ONE 0x1 |
| 28 | #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF |
| 29 | |
| 30 | #define RESERVED_AS_ZERO 0x0 |
Sieu Mun Tang | a068fdf | 2022-05-11 10:01:54 +0800 | [diff] [blame] | 31 | /* FCS Single cert */ |
| 32 | |
| 33 | #define FCS_BIG_CNTR_SEL 0x1 |
| 34 | |
| 35 | #define FCS_SVN_CNTR_0_SEL 0x2 |
| 36 | #define FCS_SVN_CNTR_1_SEL 0x3 |
| 37 | #define FCS_SVN_CNTR_2_SEL 0x4 |
| 38 | #define FCS_SVN_CNTR_3_SEL 0x5 |
| 39 | |
| 40 | #define FCS_BIG_CNTR_VAL_MAX 495U |
| 41 | #define FCS_SVN_CNTR_VAL_MAX 64U |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 42 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 43 | /* FCS Payload Structure */ |
| 44 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 45 | typedef struct fcs_encrypt_payload_t { |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 46 | uint32_t first_word; |
| 47 | uint32_t src_addr; |
| 48 | uint32_t src_size; |
| 49 | uint32_t dst_addr; |
| 50 | uint32_t dst_size; |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 51 | } fcs_encrypt_payload; |
| 52 | |
| 53 | typedef struct fcs_decrypt_payload_t { |
| 54 | uint32_t first_word; |
| 55 | uint32_t owner_id[2]; |
| 56 | uint32_t src_addr; |
| 57 | uint32_t src_size; |
| 58 | uint32_t dst_addr; |
| 59 | uint32_t dst_size; |
| 60 | } fcs_decrypt_payload; |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 61 | |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 62 | typedef struct psgsigma_teardown_msg_t { |
| 63 | uint32_t reserved_word; |
| 64 | uint32_t magic_word; |
| 65 | uint32_t session_id; |
| 66 | } psgsigma_teardown_msg; |
| 67 | |
Sieu Mun Tang | a068fdf | 2022-05-11 10:01:54 +0800 | [diff] [blame] | 68 | typedef struct fcs_cntr_set_preauth_payload_t { |
| 69 | uint32_t first_word; |
| 70 | uint32_t counter_value; |
| 71 | } fcs_cntr_set_preauth_payload; |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 72 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 73 | /* Functions Definitions */ |
| 74 | |
| 75 | uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, |
| 76 | uint32_t *mbox_error); |
| 77 | uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, |
| 78 | uint32_t *send_id); |
| 79 | uint32_t intel_fcs_get_provision_data(uint32_t *send_id); |
Sieu Mun Tang | a068fdf | 2022-05-11 10:01:54 +0800 | [diff] [blame] | 80 | uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, |
| 81 | int32_t counter_value, |
| 82 | uint32_t test_bit, |
| 83 | uint32_t *mbox_error); |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame] | 84 | uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, |
| 85 | uint32_t dst_addr, uint32_t dst_size, |
| 86 | uint32_t *send_id); |
| 87 | |
| 88 | uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, |
| 89 | uint32_t dst_addr, uint32_t dst_size, |
| 90 | uint32_t *send_id); |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 91 | |
Sieu Mun Tang | 2a820b9 | 2022-05-11 09:59:55 +0800 | [diff] [blame] | 92 | int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); |
| 93 | int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); |
| 94 | int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, |
| 95 | uint64_t dst_addr, uint32_t *dst_size, |
| 96 | uint32_t *mbox_error); |
| 97 | int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, |
| 98 | uint64_t dst_addr, uint32_t *dst_size, |
| 99 | uint32_t *mbox_error); |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 100 | uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, |
| 101 | uint32_t *mbox_error); |
| 102 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 103 | #endif /* SOCFPGA_FCS_H */ |