Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_FCS_H |
| 8 | #define SOCFPGA_FCS_H |
| 9 | |
| 10 | /* FCS Definitions */ |
| 11 | |
| 12 | #define FCS_RANDOM_WORD_SIZE 8U |
| 13 | #define FCS_PROV_DATA_WORD_SIZE 44U |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 14 | #define FCS_SHA384_WORD_SIZE 12U |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 15 | |
| 16 | #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) |
| 17 | #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 18 | #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 19 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame^] | 20 | #define FCS_MODE_DECRYPT 0x0 |
| 21 | #define FCS_MODE_ENCRYPT 0x1 |
| 22 | #define FCS_ENCRYPTION_DATA_0 0x10100 |
| 23 | #define FCS_DECRYPTION_DATA_0 0x10102 |
| 24 | #define FCS_OWNER_ID_OFFSET 0xC |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 25 | |
| 26 | /* FCS Payload Structure */ |
| 27 | |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame^] | 28 | typedef struct fcs_encrypt_payload_t { |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 29 | uint32_t first_word; |
| 30 | uint32_t src_addr; |
| 31 | uint32_t src_size; |
| 32 | uint32_t dst_addr; |
| 33 | uint32_t dst_size; |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame^] | 34 | } fcs_encrypt_payload; |
| 35 | |
| 36 | typedef struct fcs_decrypt_payload_t { |
| 37 | uint32_t first_word; |
| 38 | uint32_t owner_id[2]; |
| 39 | uint32_t src_addr; |
| 40 | uint32_t src_size; |
| 41 | uint32_t dst_addr; |
| 42 | uint32_t dst_size; |
| 43 | } fcs_decrypt_payload; |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 44 | |
| 45 | /* Functions Definitions */ |
| 46 | |
| 47 | uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, |
| 48 | uint32_t *mbox_error); |
| 49 | uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size, |
| 50 | uint32_t *send_id); |
| 51 | uint32_t intel_fcs_get_provision_data(uint32_t *send_id); |
Sieu Mun Tang | 128d2a7 | 2022-05-11 09:49:25 +0800 | [diff] [blame^] | 52 | uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, |
| 53 | uint32_t dst_addr, uint32_t dst_size, |
| 54 | uint32_t *send_id); |
| 55 | |
| 56 | uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, |
| 57 | uint32_t dst_addr, uint32_t dst_size, |
| 58 | uint32_t *send_id); |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 59 | |
Sieu Mun Tang | a34b881 | 2022-03-17 03:11:55 +0800 | [diff] [blame] | 60 | uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, |
| 61 | uint32_t *mbox_error); |
| 62 | |
Sieu Mun Tang | 9f22cbf | 2022-03-02 11:04:09 +0800 | [diff] [blame] | 63 | #endif /* SOCFPGA_FCS_H */ |