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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
Tanmay Shahfdae9e82022-08-26 15:06:00 -07003 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
Akshay Belsare589ccce2023-05-08 19:00:53 +05304 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05305 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <assert.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053010#include <errno.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053011
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <bl31/bl31.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070015#include <lib/mmio.h>
Michal Simek058251a2023-04-13 13:19:11 +020016#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <plat/common/platform.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053018#include <plat_arm.h>
Prasad Kummari4d068a42023-09-19 22:16:12 +053019#include <plat_console.h>
Prasad Kummari536e1102023-06-22 10:50:02 +053020
Amit Nagal3a7d3042023-07-10 10:32:15 +053021#include <plat_fdt.h>
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070022#include <plat_private.h>
23#include <plat_startup.h>
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053024#include "pm_api_sys.h"
Prasad Kummari536e1102023-06-22 10:50:02 +053025#include "pm_client.h"
26#include <pm_ipi.h>
27#include <versal_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053029static entry_point_info_t bl32_image_ep_info;
30static entry_point_info_t bl33_image_ep_info;
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053031
32/*
33 * Return a pointer to the 'entry_point_info' structure of the next image for
34 * the security state specified. BL33 corresponds to the non-secure image type
35 * while BL32 corresponds to the secure image type. A NULL pointer is returned
36 * if the image does not exist.
37 */
38entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
39{
40 assert(sec_state_is_valid(type));
41
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070042 if (type == NON_SECURE) {
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053043 return &bl33_image_ep_info;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070044 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053045
46 return &bl32_image_ep_info;
47}
48
49/*
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070050 * Set the build time defaults,if we can't find any config data.
51 */
52static inline void bl31_set_default_config(void)
53{
Abhyuday Godhasarac0c49e52021-08-24 07:39:41 -070054 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
55 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry();
56 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint();
57 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
58 DISABLE_ALL_EXCEPTIONS);
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070059}
60
61/*
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053062 * Perform any BL31 specific platform actions. Here is an opportunity to copy
63 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
64 * are lost (potentially). This needs to be done before the MMU is initialized
65 * so that the memory layout can be used while creating page tables.
66 */
67void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
68 u_register_t arg2, u_register_t arg3)
69{
Prasad Kummarie0783112023-04-26 11:02:07 +053070 uint64_t tfa_handoff_addr;
Prasad Kummari07795fa2023-06-08 21:36:38 +053071 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE;
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053072 enum pm_ret_status ret_status;
Prasad Kummari07795fa2023-06-08 21:36:38 +053073 uint64_t addr[HANDOFF_PARAMS_MAX_SIZE];
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053074
Prasad Kummari4d068a42023-09-19 22:16:12 +053075 setup_console();
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -070076
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053077 /* Initialize the platform config for future decision making */
78 versal_config_setup();
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053079
Akshay Belsare589ccce2023-05-08 19:00:53 +053080 /* Get platform related information */
81 board_detection();
82
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053083 /*
84 * Do initial security configuration to allow DRAM/device access. On
85 * Base VERSAL only DRAM security is programmable (via TrustZone), but
86 * other platforms might have more programmable security devices
87 * present.
88 */
89
90 /* Populate common information for BL32 and BL33 */
91 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
92 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
93 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
94 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
95
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053096 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS,
97 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size);
98 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
99 if (ret_status == PM_RET_SUCCESS) {
100 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status);
Prasad Kummarie0783112023-04-26 11:02:07 +0530101 tfa_handoff_addr = (uintptr_t)&addr;
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530102 } else {
Prasad Kummarie0783112023-04-26 11:02:07 +0530103 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n");
104 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530105 }
106
Prasad Kummari07795fa2023-06-08 21:36:38 +0530107 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info,
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700108 &bl33_image_ep_info,
Prasad Kummarie0783112023-04-26 11:02:07 +0530109 tfa_handoff_addr);
Prasad Kummari07795fa2023-06-08 21:36:38 +0530110 if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) {
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700111 bl31_set_default_config();
Prasad Kummari07795fa2023-06-08 21:36:38 +0530112 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) {
Venkatesh Yadav Abbarapu39fdc0a2022-03-03 01:58:36 -0700113 ERROR("BL31: Error too many partitions %u\n", ret);
Prasad Kummari07795fa2023-06-08 21:36:38 +0530114 } else if (ret != XBL_HANDOFF_SUCCESS) {
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700115 panic();
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -0700116 } else {
Akshay Belsaree3511ae2023-01-11 11:45:25 +0530117 INFO("BL31: PLM to TF-A handover success %u\n", ret);
Prasad Kummari6dee9fb2023-10-31 15:20:00 +0530118
119 /*
120 * The BL32 load address is indicated as 0x0 in the handoff
121 * parameters, which is different from the default/user-provided
122 * load address of 0x60000000 but the flags are correctly
123 * configured. Consequently, in this scenario, set the PC
124 * to the requested BL32_BASE address.
125 */
126
127 /* TODO: Remove the following check once this is fixed from PLM */
128 if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) {
129 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
130 }
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700131 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530132
133 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
134 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
135}
136
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700137static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530138
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700139int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530140{
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700141 static uint32_t index;
142 uint32_t i;
143
144 /* Validate 'handler' and 'id' parameters */
145 if (handler == NULL || index >= MAX_INTR_EL3) {
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530146 return -EINVAL;
147 }
148
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700149 /* Check if a handler has already been registered */
150 for (i = 0; i < index; i++) {
151 if (id == type_el3_interrupt_table[i].id) {
152 return -EALREADY;
153 }
154 }
155
156 type_el3_interrupt_table[index].id = id;
157 type_el3_interrupt_table[index].handler = handler;
158
159 index++;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530160
161 return 0;
162}
163
164static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
165 void *handle, void *cookie)
166{
167 uint32_t intr_id;
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700168 uint32_t i;
169 interrupt_type_handler_t handler = NULL;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530170
171 intr_id = plat_ic_get_pending_interrupt_id();
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530172
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700173 for (i = 0; i < MAX_INTR_EL3; i++) {
174 if (intr_id == type_el3_interrupt_table[i].id) {
175 handler = type_el3_interrupt_table[i].handler;
176 }
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530177 }
178
Michal Simek5e2f5962022-09-13 11:48:53 +0200179 if (handler != NULL) {
180 return handler(intr_id, flags, handle, cookie);
181 }
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700182
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530183 return 0;
184}
Amit Nagal3a7d3042023-07-10 10:32:15 +0530185
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530186void bl31_platform_setup(void)
187{
Amit Nagal3a7d3042023-07-10 10:32:15 +0530188 prepare_dtb();
189
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530190 /* Initialize the gic cpu and distributor interfaces */
191 plat_versal_gic_driver_init();
192 plat_versal_gic_init();
193}
194
195void bl31_plat_runtime_setup(void)
196{
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530197 uint64_t flags = 0;
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700198 int32_t rc;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530199
200 set_interrupt_rm_flag(flags, NON_SECURE);
201 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
202 rdo_el3_interrupt_handler, flags);
Abhyuday Godhasarabacbdee2021-08-20 00:27:03 -0700203 if (rc != 0) {
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530204 panic();
205 }
Michal Simek3da80c82023-10-13 11:12:19 +0200206
207 console_switch_state(CONSOLE_FLAG_RUNTIME);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530208}
209
210/*
211 * Perform the very early platform specific architectural setup here.
212 */
213void bl31_plat_arch_setup(void)
214{
Tejas Patel54d13192019-02-27 18:44:55 +0530215 plat_arm_interconnect_init();
216 plat_arm_interconnect_enter_coherency();
217
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530218 const mmap_region_t bl_regions[] = {
Amit Nagalc1248e82023-09-04 21:53:59 -1200219#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \
220 (!defined(PLAT_XLAT_TABLES_DYNAMIC)))
Amit Nagal3a7d3042023-07-10 10:32:15 +0530221 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
222 MT_MEMORY | MT_RW | MT_NS),
223#endif
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530224 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
225 MT_MEMORY | MT_RW | MT_SECURE),
226 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
227 MT_CODE | MT_SECURE),
228 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
229 MT_RO_DATA | MT_SECURE),
230 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
231 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
232 MT_DEVICE | MT_RW | MT_SECURE),
233 {0}
234 };
235
Prasad Kummari0b377142023-10-26 16:32:26 +0530236 setup_page_tables(bl_regions, plat_get_mmap());
Michal Simek058251a2023-04-13 13:19:11 +0200237 enable_mmu(0);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530238}