Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 1 | /* |
Govindraj Raja | eee28e7 | 2023-08-01 15:52:40 -0500 | [diff] [blame] | 2 | * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. |
Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 7 | #ifndef CORTEX_A77_H |
| 8 | #define CORTEX_A77_H |
Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 12 | /* Cortex-A77 MIDR */ |
| 13 | #define CORTEX_A77_MIDR U(0x410FD0D0) |
Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 14 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 15 | /* Cortex-A77 loop count for CVE-2022-23960 mitigation */ |
| 16 | #define CORTEX_A77_BHB_LOOP_COUNT U(24) |
| 17 | |
Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 18 | /******************************************************************************* |
| 19 | * CPU Extended Control register specific definitions. |
| 20 | ******************************************************************************/ |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 21 | #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 |
johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 22 | #define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) |
Boyan Karatotev | e5cf16b | 2022-09-27 10:37:54 +0100 | [diff] [blame] | 23 | #define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) |
Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 24 | |
| 25 | /******************************************************************************* |
| 26 | * CPU Power Control register specific definitions. |
| 27 | ******************************************************************************/ |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 28 | #define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 29 | #define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) |
Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 30 | |
johpow01 | eb14610 | 2021-05-03 13:37:13 -0500 | [diff] [blame] | 31 | /******************************************************************************* |
| 32 | * CPU Auxiliary Control register specific definitions. |
| 33 | ******************************************************************************/ |
| 34 | #define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1 |
| 35 | #define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2) |
Bipin Ravi | 8e91662 | 2022-06-08 15:27:00 -0500 | [diff] [blame] | 36 | #define CORTEX_A77_ACTLR2_EL1_BIT_0 ULL(1) |
johpow01 | eb14610 | 2021-05-03 13:37:13 -0500 | [diff] [blame] | 37 | |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 38 | #define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0 |
| 39 | #define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1 |
| 40 | #define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2 |
| 41 | #define CORTEX_A77_CPUPMR_EL3 S3_6_C15_C8_3 |
| 42 | #define CORTEX_A77_CPUPOR2_EL3 S3_6_C15_C8_4 |
| 43 | #define CORTEX_A77_CPUPMR2_EL3 S3_6_C15_C8_5 |
| 44 | |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 45 | #endif /* CORTEX_A77_H */ |