| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_DEIMOS_H |
| 8 | #define CORTEX_DEIMOS_H |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 9 | |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame^] | 10 | #include <lib/utils_def.h> |
| 11 | |
| Joel Hutton | 9463cae | 2018-05-04 15:09:47 +0100 | [diff] [blame] | 12 | #define CORTEX_DEIMOS_MIDR U(0x410FD0D0) |
| 13 | |
| 14 | /******************************************************************************* |
| 15 | * CPU Extended Control register specific definitions. |
| 16 | ******************************************************************************/ |
| 17 | #define CORTEX_DEIMOS_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 18 | |
| 19 | /******************************************************************************* |
| 20 | * CPU Power Control register specific definitions. |
| 21 | ******************************************************************************/ |
| 22 | #define CORTEX_DEIMOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 23 | #define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) |
| 24 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 25 | #endif /* CORTEX_DEIMOS_H */ |