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Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05301/*
Michal Simek2a47faa2023-04-14 08:43:51 +02002 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
Tanmay Shahfdae9e82022-08-26 15:06:00 -07003 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
Akshay Belsare589ccce2023-05-08 19:00:53 +05304 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +05305 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <assert.h>
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053010#include <errno.h>
Tejas Patel54d13192019-02-27 18:44:55 +053011#include <plat_arm.h>
Tejas Patel69409962018-12-14 00:55:29 -080012#include <plat_private.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <bl31/bl31.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070016#include <drivers/arm/dcc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <drivers/arm/pl011.h>
18#include <drivers/console.h>
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070019#include <lib/mmio.h>
Michal Simek058251a2023-04-13 13:19:11 +020020#include <lib/xlat_tables/xlat_tables_v2.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <plat/common/platform.h>
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070022#include <versal_def.h>
23#include <plat_private.h>
24#include <plat_startup.h>
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053025#include <pm_ipi.h>
26#include "pm_client.h"
27#include "pm_api_sys.h"
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053029static entry_point_info_t bl32_image_ep_info;
30static entry_point_info_t bl33_image_ep_info;
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053031
32/*
33 * Return a pointer to the 'entry_point_info' structure of the next image for
34 * the security state specified. BL33 corresponds to the non-secure image type
35 * while BL32 corresponds to the secure image type. A NULL pointer is returned
36 * if the image does not exist.
37 */
38entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
39{
40 assert(sec_state_is_valid(type));
41
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070042 if (type == NON_SECURE) {
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053043 return &bl33_image_ep_info;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070044 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053045
46 return &bl32_image_ep_info;
47}
48
49/*
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070050 * Set the build time defaults,if we can't find any config data.
51 */
52static inline void bl31_set_default_config(void)
53{
Abhyuday Godhasarac0c49e52021-08-24 07:39:41 -070054 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
55 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry();
56 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint();
57 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
58 DISABLE_ALL_EXCEPTIONS);
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -070059}
60
61/*
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053062 * Perform any BL31 specific platform actions. Here is an opportunity to copy
63 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
64 * are lost (potentially). This needs to be done before the MMU is initialized
65 * so that the memory layout can be used while creating page tables.
66 */
67void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
68 u_register_t arg2, u_register_t arg3)
69{
Prasad Kummarie0783112023-04-26 11:02:07 +053070 uint64_t tfa_handoff_addr;
71 uint32_t payload[PAYLOAD_ARG_CNT], max_size = TFA_HANDOFF_PARAMS_MAX_SIZE;
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +053072 enum pm_ret_status ret_status;
Prasad Kummarie0783112023-04-26 11:02:07 +053073 uint64_t addr[TFA_HANDOFF_PARAMS_MAX_SIZE];
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053074
Venkatesh Yadav Abbarapue91b4c22021-12-19 21:36:23 -070075 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) {
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070076 static console_t versal_runtime_console;
77 /* Initialize the console to provide early debug support */
Venkatesh Yadav Abbarapu2cefbcd2022-07-31 14:05:40 +053078 int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE,
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053079 (uint32_t)VERSAL_UART_CLOCK,
80 (uint32_t)VERSAL_UART_BAUDRATE,
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070081 &versal_runtime_console);
82 if (rc == 0) {
83 panic();
84 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053085
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053086 console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT |
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -070087 CONSOLE_FLAG_RUNTIME));
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070088 } else if (VERSAL_CONSOLE_IS(dcc)) {
89 /* Initialize the dcc console for debug */
Venkatesh Yadav Abbarapubde87592022-05-24 11:11:12 +053090 int32_t rc = console_dcc_register();
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070091 if (rc == 0) {
92 panic();
93 }
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -070094 } else {
95 NOTICE("BL31: Did not register for any console.\n");
Venkatesh Yadav Abbarapu17a12ce2020-11-27 08:42:14 -070096 }
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -070097
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +053098 /* Initialize the platform config for future decision making */
99 versal_config_setup();
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530100
Akshay Belsare589ccce2023-05-08 19:00:53 +0530101 /* Get platform related information */
102 board_detection();
103
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530104 /*
105 * Do initial security configuration to allow DRAM/device access. On
106 * Base VERSAL only DRAM security is programmable (via TrustZone), but
107 * other platforms might have more programmable security devices
108 * present.
109 */
110
111 /* Populate common information for BL32 and BL33 */
112 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
113 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
114 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
115 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
116
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530117 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS,
118 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size);
119 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
120 if (ret_status == PM_RET_SUCCESS) {
121 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status);
Prasad Kummarie0783112023-04-26 11:02:07 +0530122 tfa_handoff_addr = (uintptr_t)&addr;
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530123 } else {
Prasad Kummarie0783112023-04-26 11:02:07 +0530124 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n");
125 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4);
Venkatesh Yadav Abbarapu58b24d82022-07-12 09:19:03 +0530126 }
127
Prasad Kummarie0783112023-04-26 11:02:07 +0530128 enum fsbl_handoff ret = fsbl_tfa_handover(&bl32_image_ep_info,
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700129 &bl33_image_ep_info,
Prasad Kummarie0783112023-04-26 11:02:07 +0530130 tfa_handoff_addr);
Venkatesh Yadav Abbarapuef75de02020-11-23 03:29:51 -0800131 if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) {
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700132 bl31_set_default_config();
Venkatesh Yadav Abbarapu39fdc0a2022-03-03 01:58:36 -0700133 } else if (ret == FSBL_HANDOFF_TOO_MANY_PARTS) {
134 ERROR("BL31: Error too many partitions %u\n", ret);
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700135 } else if (ret != FSBL_HANDOFF_SUCCESS) {
136 panic();
Abhyuday Godhasara4c1a7052021-08-11 02:52:35 -0700137 } else {
Akshay Belsaree3511ae2023-01-11 11:45:25 +0530138 INFO("BL31: PLM to TF-A handover success %u\n", ret);
Venkatesh Yadav Abbarapu9156ffd2020-01-22 21:23:20 -0700139 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530140
141 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
142 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
143}
144
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700145static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530146
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700147int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530148{
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700149 static uint32_t index;
150 uint32_t i;
151
152 /* Validate 'handler' and 'id' parameters */
153 if (handler == NULL || index >= MAX_INTR_EL3) {
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530154 return -EINVAL;
155 }
156
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700157 /* Check if a handler has already been registered */
158 for (i = 0; i < index; i++) {
159 if (id == type_el3_interrupt_table[i].id) {
160 return -EALREADY;
161 }
162 }
163
164 type_el3_interrupt_table[index].id = id;
165 type_el3_interrupt_table[index].handler = handler;
166
167 index++;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530168
169 return 0;
170}
171
172static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
173 void *handle, void *cookie)
174{
175 uint32_t intr_id;
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700176 uint32_t i;
177 interrupt_type_handler_t handler = NULL;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530178
179 intr_id = plat_ic_get_pending_interrupt_id();
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530180
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700181 for (i = 0; i < MAX_INTR_EL3; i++) {
182 if (intr_id == type_el3_interrupt_table[i].id) {
183 handler = type_el3_interrupt_table[i].handler;
184 }
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530185 }
186
Michal Simek5e2f5962022-09-13 11:48:53 +0200187 if (handler != NULL) {
188 return handler(intr_id, flags, handle, cookie);
189 }
Tanmay Shahfdae9e82022-08-26 15:06:00 -0700190
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530191 return 0;
192}
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530193void bl31_platform_setup(void)
194{
195 /* Initialize the gic cpu and distributor interfaces */
196 plat_versal_gic_driver_init();
197 plat_versal_gic_init();
198}
199
200void bl31_plat_runtime_setup(void)
201{
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530202 uint64_t flags = 0;
Abhyuday Godhasara096f5cc2021-08-13 06:45:32 -0700203 int32_t rc;
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530204
205 set_interrupt_rm_flag(flags, NON_SECURE);
206 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
207 rdo_el3_interrupt_handler, flags);
Abhyuday Godhasarabacbdee2021-08-20 00:27:03 -0700208 if (rc != 0) {
Shubhrajyoti Dattaabf61222021-03-17 23:01:17 +0530209 panic();
210 }
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530211}
212
213/*
214 * Perform the very early platform specific architectural setup here.
215 */
216void bl31_plat_arch_setup(void)
217{
Tejas Patel54d13192019-02-27 18:44:55 +0530218 plat_arm_interconnect_init();
219 plat_arm_interconnect_enter_coherency();
220
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530221 const mmap_region_t bl_regions[] = {
222 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
223 MT_MEMORY | MT_RW | MT_SECURE),
224 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
225 MT_CODE | MT_SECURE),
226 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
227 MT_RO_DATA | MT_SECURE),
228 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
229 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
230 MT_DEVICE | MT_RW | MT_SECURE),
231 {0}
232 };
233
234 setup_page_tables(bl_regions, plat_versal_get_mmap());
Michal Simek058251a2023-04-13 13:19:11 +0200235 enable_mmu(0);
Siva Durga Prasad Paladugufe4af662018-09-25 18:44:58 +0530236}