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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#ifndef __ARCH_H__
8#define __ARCH_H__
9
Scott Brandenbf404c02017-04-10 11:45:52 -070010#include <utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
12/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(0x18)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_VAR_MASK U(0xf)
20#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
22#define MIDR_REV_MASK U(0xf)
23#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070029#define MPIDR_MT_MASK (U(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070031#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32#define MPIDR_AFFINITY_BITS U(8)
33#define MPIDR_AFFLVL_MASK U(0xff)
34#define MPIDR_AFF0_SHIFT U(0)
35#define MPIDR_AFF1_SHIFT U(8)
36#define MPIDR_AFF2_SHIFT U(16)
37#define MPIDR_AFF3_SHIFT U(32)
38#define MPIDR_AFFINITY_MASK U(0xff00ffffff)
39#define MPIDR_AFFLVL_SHIFT U(3)
40#define MPIDR_AFFLVL0 U(0)
41#define MPIDR_AFFLVL1 U(1)
42#define MPIDR_AFFLVL2 U(2)
43#define MPIDR_AFFLVL3 U(3)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000044#define MPIDR_AFFLVL0_VAL(mpidr) \
45 ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
46#define MPIDR_AFFLVL1_VAL(mpidr) \
47 ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
48#define MPIDR_AFFLVL2_VAL(mpidr) \
49 ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
50#define MPIDR_AFFLVL3_VAL(mpidr) \
51 ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000052/*
53 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
54 * add one while using this macro to define array sizes.
55 * TODO: Support only the first 3 affinity levels for now.
56 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070057#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010058
59/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define FIRST_MPIDR U(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
62/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010063 * Definitions for CPU system register interface to GICv3
64 ******************************************************************************/
65#define ICC_SRE_EL1 S3_0_C12_C12_5
66#define ICC_SRE_EL2 S3_4_C12_C9_5
67#define ICC_SRE_EL3 S3_6_C12_C12_5
68#define ICC_CTLR_EL1 S3_0_C12_C12_4
69#define ICC_CTLR_EL3 S3_6_C12_C12_4
70#define ICC_PMR_EL1 S3_0_C4_C6_0
Achin Gupta92712a52015-09-03 14:18:02 +010071#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
72#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
73#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
74#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
75#define ICC_IAR0_EL1 S3_0_c12_c8_0
76#define ICC_IAR1_EL1 S3_0_c12_c12_0
77#define ICC_EOIR0_EL1 S3_0_c12_c8_1
78#define ICC_EOIR1_EL1 S3_0_c12_c12_1
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010079
80/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000081 * Generic timer memory mapped registers & offsets
82 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070083#define CNTCR_OFF U(0x000)
84#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +000085
Varun Wadekarc6a11f62017-05-25 18:04:48 -070086#define CNTCR_EN (U(1) << 0)
87#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +010088#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +000089
90/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010091 * System register bit definitions
92 ******************************************************************************/
93/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070094#define LOUIS_SHIFT U(21)
95#define LOC_SHIFT U(24)
96#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +010097
98/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070099#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100
101/* D$ set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700102#define DCISW U(0x0)
103#define DCCISW U(0x1)
104#define DCCSW U(0x2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105
106/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700107#define ID_AA64PFR0_EL0_SHIFT U(0)
108#define ID_AA64PFR0_EL1_SHIFT U(4)
109#define ID_AA64PFR0_EL2_SHIFT U(8)
110#define ID_AA64PFR0_EL3_SHIFT U(12)
111#define ID_AA64PFR0_ELX_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112
dp-armee3457b2017-05-23 09:32:49 +0100113/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
114#define ID_AA64DFR0_PMS_SHIFT U(32)
115#define ID_AA64DFR0_PMS_LENGTH U(4)
116#define ID_AA64DFR0_PMS_MASK U(0xf)
117
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700118#define EL_IMPL_NONE U(0)
119#define EL_IMPL_A64ONLY U(1)
120#define EL_IMPL_A64_A32 U(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000121
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700122#define ID_AA64PFR0_GIC_SHIFT U(24)
123#define ID_AA64PFR0_GIC_WIDTH U(4)
124#define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1)
Achin Gupta92712a52015-09-03 14:18:02 +0100125
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000126/* ID_AA64MMFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700127#define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000128
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700129#define PARANGE_0000 U(32)
130#define PARANGE_0001 U(36)
131#define PARANGE_0010 U(40)
132#define PARANGE_0011 U(42)
133#define PARANGE_0100 U(44)
134#define PARANGE_0101 U(48)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000135
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700137#define ID_PFR1_VIRTEXT_SHIFT U(12)
138#define ID_PFR1_VIRTEXT_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
140 & ID_PFR1_VIRTEXT_MASK)
141
142/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100143#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700144 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
145 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146
David Cunadofee86532017-04-13 22:38:29 +0100147#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700148 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200149#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700150 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
151 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200152
David Cunadofee86532017-04-13 22:38:29 +0100153#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
154 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
155 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
156
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700157#define SCTLR_M_BIT (U(1) << 0)
158#define SCTLR_A_BIT (U(1) << 1)
159#define SCTLR_C_BIT (U(1) << 2)
160#define SCTLR_SA_BIT (U(1) << 3)
161#define SCTLR_CP15BEN_BIT (U(1) << 5)
162#define SCTLR_I_BIT (U(1) << 12)
163#define SCTLR_NTWI_BIT (U(1) << 16)
164#define SCTLR_NTWE_BIT (U(1) << 18)
165#define SCTLR_WXN_BIT (U(1) << 19)
166#define SCTLR_EE_BIT (U(1) << 25)
David Cunadofee86532017-04-13 22:38:29 +0100167#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168
Achin Gupta4f6ad662013-10-25 09:08:21 +0100169/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700170#define CPACR_EL1_FPEN(x) ((x) << 20)
171#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
172#define CPACR_EL1_FP_TRAP_ALL U(0x2)
173#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174
175/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700176#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
177#define SCR_TWE_BIT (U(1) << 13)
178#define SCR_TWI_BIT (U(1) << 12)
179#define SCR_ST_BIT (U(1) << 11)
180#define SCR_RW_BIT (U(1) << 10)
181#define SCR_SIF_BIT (U(1) << 9)
182#define SCR_HCE_BIT (U(1) << 8)
183#define SCR_SMD_BIT (U(1) << 7)
184#define SCR_EA_BIT (U(1) << 3)
185#define SCR_FIQ_BIT (U(1) << 2)
186#define SCR_IRQ_BIT (U(1) << 1)
187#define SCR_NS_BIT (U(1) << 0)
188#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100189#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190
David Cunadofee86532017-04-13 22:38:29 +0100191/* MDCR_EL3 definitions */
dp-arm595d0d52017-02-08 11:51:50 +0000192#define MDCR_SPD32(x) ((x) << 14)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700193#define MDCR_SPD32_LEGACY U(0x0)
194#define MDCR_SPD32_DISABLE U(0x2)
195#define MDCR_SPD32_ENABLE U(0x3)
196#define MDCR_SDD_BIT (U(1) << 16)
dp-armee3457b2017-05-23 09:32:49 +0100197#define MDCR_NSPB(x) ((x) << 12)
198#define MDCR_NSPB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100199#define MDCR_TDOSA_BIT (U(1) << 10)
200#define MDCR_TDA_BIT (U(1) << 9)
201#define MDCR_TPM_BIT (U(1) << 6)
202#define MDCR_EL3_RESET_VAL U(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000203
David Cunadofee86532017-04-13 22:38:29 +0100204#if !ERROR_DEPRECATED
dp-arm595d0d52017-02-08 11:51:50 +0000205#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
David Cunadofee86532017-04-13 22:38:29 +0100206#endif
207
208/* MDCR_EL2 definitions */
dp-armee3457b2017-05-23 09:32:49 +0100209#define MDCR_EL2_TPMS (U(1) << 14)
210#define MDCR_EL2_E2PB(x) ((x) << 12)
211#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100212#define MDCR_EL2_TDRA_BIT (U(1) << 11)
213#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
214#define MDCR_EL2_TDA_BIT (U(1) << 9)
215#define MDCR_EL2_TDE_BIT (U(1) << 8)
216#define MDCR_EL2_HPME_BIT (U(1) << 7)
217#define MDCR_EL2_TPM_BIT (U(1) << 6)
218#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
219#define MDCR_EL2_RESET_VAL U(0x0)
220
221/* HSTR_EL2 definitions */
222#define HSTR_EL2_RESET_VAL U(0x0)
223#define HSTR_EL2_T_MASK U(0xff)
224
225/* CNTHP_CTL_EL2 definitions */
226#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
227#define CNTHP_CTL_RESET_VAL U(0x0)
228
229/* VTTBR_EL2 definitions */
230#define VTTBR_RESET_VAL ULL(0x0)
231#define VTTBR_VMID_MASK ULL(0xff)
232#define VTTBR_VMID_SHIFT U(48)
233#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
234#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000235
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236/* HCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700237#define HCR_RW_SHIFT U(31)
238#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
239#define HCR_AMO_BIT (U(1) << 5)
240#define HCR_IMO_BIT (U(1) << 4)
241#define HCR_FMO_BIT (U(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100243/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700244#define ISR_A_SHIFT U(8)
245#define ISR_I_SHIFT U(7)
246#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100247
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100249#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700250#define EVNTEN_BIT (U(1) << 2)
251#define EL1PCEN_BIT (U(1) << 1)
252#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100253
254/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700255#define EL0PTEN_BIT (U(1) << 9)
256#define EL0VTEN_BIT (U(1) << 8)
257#define EL0PCTEN_BIT (U(1) << 0)
258#define EL0VCTEN_BIT (U(1) << 1)
259#define EVNTEN_BIT (U(1) << 2)
260#define EVNTDIR_BIT (U(1) << 3)
261#define EVNTI_SHIFT U(4)
262#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100263
264/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700265#define TCPAC_BIT (U(1) << 31)
266#define TTA_BIT (U(1) << 20)
267#define TFP_BIT (U(1) << 10)
David Cunadofee86532017-04-13 22:38:29 +0100268#define CPTR_EL3_RESET_VAL U(0x0)
269
270/* CPTR_EL2 definitions */
271#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
272#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
273#define CPTR_EL2_TTA_BIT (U(1) << 20)
274#define CPTR_EL2_TFP_BIT (U(1) << 10)
275#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276
277/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700278#define DAIF_FIQ_BIT (U(1) << 0)
279#define DAIF_IRQ_BIT (U(1) << 1)
280#define DAIF_ABT_BIT (U(1) << 2)
281#define DAIF_DBG_BIT (U(1) << 3)
282#define SPSR_DAIF_SHIFT U(6)
283#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100284
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700285#define SPSR_AIF_SHIFT U(6)
286#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100287
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700288#define SPSR_E_SHIFT U(9)
289#define SPSR_E_MASK U(0x1)
290#define SPSR_E_LITTLE U(0x0)
291#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100292
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700293#define SPSR_T_SHIFT U(5)
294#define SPSR_T_MASK U(0x1)
295#define SPSR_T_ARM U(0x0)
296#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100297
298#define DISABLE_ALL_EXCEPTIONS \
299 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
300
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000301/*
302 * RMR_EL3 definitions
303 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700304#define RMR_EL3_RR_BIT (U(1) << 1)
305#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000306
307/*
308 * HI-VECTOR address for AArch32 state
309 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700310#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311
312/*
313 * TCR defintions
314 */
315#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700316#define TCR_EL1_IPS_SHIFT U(32)
317#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700318
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700319#define TCR_TxSZ_MIN U(16)
320#define TCR_TxSZ_MAX U(39)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100321
Lin Ma741a3822014-06-27 16:56:30 -0700322/* (internal) physical address size bits in EL3/EL1 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700323#define TCR_PS_BITS_4GB U(0x0)
324#define TCR_PS_BITS_64GB U(0x1)
325#define TCR_PS_BITS_1TB U(0x2)
326#define TCR_PS_BITS_4TB U(0x3)
327#define TCR_PS_BITS_16TB U(0x4)
328#define TCR_PS_BITS_256TB U(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100329
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700330#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
331#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
332#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
333#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
334#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
335#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100336
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700337#define TCR_RGN_INNER_NC (U(0x0) << 8)
338#define TCR_RGN_INNER_WBA (U(0x1) << 8)
339#define TCR_RGN_INNER_WT (U(0x2) << 8)
340#define TCR_RGN_INNER_WBNA (U(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100341
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700342#define TCR_RGN_OUTER_NC (U(0x0) << 10)
343#define TCR_RGN_OUTER_WBA (U(0x1) << 10)
344#define TCR_RGN_OUTER_WT (U(0x2) << 10)
345#define TCR_RGN_OUTER_WBNA (U(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100346
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700347#define TCR_SH_NON_SHAREABLE (U(0x0) << 12)
348#define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12)
349#define TCR_SH_INNER_SHAREABLE (U(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100350
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700351#define MODE_SP_SHIFT U(0x0)
352#define MODE_SP_MASK U(0x1)
353#define MODE_SP_EL0 U(0x0)
354#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100355
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700356#define MODE_RW_SHIFT U(0x4)
357#define MODE_RW_MASK U(0x1)
358#define MODE_RW_64 U(0x0)
359#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100360
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700361#define MODE_EL_SHIFT U(0x2)
362#define MODE_EL_MASK U(0x3)
363#define MODE_EL3 U(0x3)
364#define MODE_EL2 U(0x2)
365#define MODE_EL1 U(0x1)
366#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100367
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700368#define MODE32_SHIFT U(0)
369#define MODE32_MASK U(0xf)
370#define MODE32_usr U(0x0)
371#define MODE32_fiq U(0x1)
372#define MODE32_irq U(0x2)
373#define MODE32_svc U(0x3)
374#define MODE32_mon U(0x6)
375#define MODE32_abt U(0x7)
376#define MODE32_hyp U(0xa)
377#define MODE32_und U(0xb)
378#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100379
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100380#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
381#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
382#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
383#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100384
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100385#define SPSR_64(el, sp, daif) \
386 (MODE_RW_64 << MODE_RW_SHIFT | \
387 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
388 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
389 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
390
391#define SPSR_MODE32(mode, isa, endian, aif) \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700392 ((MODE_RW_32 << MODE_RW_SHIFT) | \
393 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
394 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
395 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
396 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397
Dan Handley0cdebbd2015-03-30 17:15:16 +0100398/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100399 * TTBR Definitions
400 */
401#define TTBR_CNP_BIT 0x1
402
403/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100404 * CTR_EL0 definitions
405 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700406#define CTR_CWG_SHIFT U(24)
407#define CTR_CWG_MASK U(0xf)
408#define CTR_ERG_SHIFT U(20)
409#define CTR_ERG_MASK U(0xf)
410#define CTR_DMINLINE_SHIFT U(16)
411#define CTR_DMINLINE_MASK U(0xf)
412#define CTR_L1IP_SHIFT U(14)
413#define CTR_L1IP_MASK U(0x3)
414#define CTR_IMINLINE_SHIFT U(0)
415#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100416
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700417#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100418
Achin Gupta405406d2014-05-09 12:00:17 +0100419/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700420#define CNTP_CTL_ENABLE_SHIFT U(0)
421#define CNTP_CTL_IMASK_SHIFT U(1)
422#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100423
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700424#define CNTP_CTL_ENABLE_MASK U(1)
425#define CNTP_CTL_IMASK_MASK U(1)
426#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100427
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700428#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100429 CNTP_CTL_ENABLE_MASK)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700430#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100431 CNTP_CTL_IMASK_MASK)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700432#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
Achin Gupta405406d2014-05-09 12:00:17 +0100433 CNTP_CTL_ISTATUS_MASK)
434
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700435#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
436#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
Achin Gupta405406d2014-05-09 12:00:17 +0100437
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700438#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
439#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
Achin Gupta405406d2014-05-09 12:00:17 +0100440
Achin Gupta4f6ad662013-10-25 09:08:21 +0100441/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700442#define ESR_EC_SHIFT U(26)
443#define ESR_EC_MASK U(0x3f)
444#define ESR_EC_LENGTH U(6)
445#define EC_UNKNOWN U(0x0)
446#define EC_WFE_WFI U(0x1)
447#define EC_AARCH32_CP15_MRC_MCR U(0x3)
448#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
449#define EC_AARCH32_CP14_MRC_MCR U(0x5)
450#define EC_AARCH32_CP14_LDC_STC U(0x6)
451#define EC_FP_SIMD U(0x7)
452#define EC_AARCH32_CP10_MRC U(0x8)
453#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
454#define EC_ILLEGAL U(0xe)
455#define EC_AARCH32_SVC U(0x11)
456#define EC_AARCH32_HVC U(0x12)
457#define EC_AARCH32_SMC U(0x13)
458#define EC_AARCH64_SVC U(0x15)
459#define EC_AARCH64_HVC U(0x16)
460#define EC_AARCH64_SMC U(0x17)
461#define EC_AARCH64_SYS U(0x18)
462#define EC_IABORT_LOWER_EL U(0x20)
463#define EC_IABORT_CUR_EL U(0x21)
464#define EC_PC_ALIGN U(0x22)
465#define EC_DABORT_LOWER_EL U(0x24)
466#define EC_DABORT_CUR_EL U(0x25)
467#define EC_SP_ALIGN U(0x26)
468#define EC_AARCH32_FP U(0x28)
469#define EC_AARCH64_FP U(0x2c)
470#define EC_SERROR U(0x2f)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100471
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700472#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100473
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800474/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700475#define RMR_RESET_REQUEST_SHIFT U(0x1)
476#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800477
Dan Handleyed6ff952014-05-14 17:44:19 +0100478/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000479 * Definitions of register offsets, fields and macros for CPU system
480 * instructions.
481 ******************************************************************************/
482
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700483#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000484#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
485#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
486
487/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100488 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
489 * system level implementation of the Generic Timer.
490 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700491#define CNTNSAR U(0x4)
492#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100493
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700494#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
495#define CNTACR_RPCT_SHIFT U(0x0)
496#define CNTACR_RVCT_SHIFT U(0x1)
497#define CNTACR_RFRQ_SHIFT U(0x2)
498#define CNTACR_RVOFF_SHIFT U(0x3)
499#define CNTACR_RWVT_SHIFT U(0x4)
500#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100501
David Cunado5f55e282016-10-31 17:37:34 +0000502/* PMCR_EL0 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700503#define PMCR_EL0_N_SHIFT U(11)
504#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000505#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
506
Isla Mitchell02c63072017-07-21 14:44:36 +0100507/*******************************************************************************
508 * Definitions of MAIR encodings for device and normal memory
509 ******************************************************************************/
510/*
511 * MAIR encodings for device memory attributes.
512 */
513#define MAIR_DEV_nGnRnE ULL(0x0)
514#define MAIR_DEV_nGnRE ULL(0x4)
515#define MAIR_DEV_nGRE ULL(0x8)
516#define MAIR_DEV_GRE ULL(0xc)
517
518/*
519 * MAIR encodings for normal memory attributes.
520 *
521 * Cache Policy
522 * WT: Write Through
523 * WB: Write Back
524 * NC: Non-Cacheable
525 *
526 * Transient Hint
527 * NTR: Non-Transient
528 * TR: Transient
529 *
530 * Allocation Policy
531 * RA: Read Allocate
532 * WA: Write Allocate
533 * RWA: Read and Write Allocate
534 * NA: No Allocation
535 */
536#define MAIR_NORM_WT_TR_WA ULL(0x1)
537#define MAIR_NORM_WT_TR_RA ULL(0x2)
538#define MAIR_NORM_WT_TR_RWA ULL(0x3)
539#define MAIR_NORM_NC ULL(0x4)
540#define MAIR_NORM_WB_TR_WA ULL(0x5)
541#define MAIR_NORM_WB_TR_RA ULL(0x6)
542#define MAIR_NORM_WB_TR_RWA ULL(0x7)
543#define MAIR_NORM_WT_NTR_NA ULL(0x8)
544#define MAIR_NORM_WT_NTR_WA ULL(0x9)
545#define MAIR_NORM_WT_NTR_RA ULL(0xa)
546#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
547#define MAIR_NORM_WB_NTR_NA ULL(0xc)
548#define MAIR_NORM_WB_NTR_WA ULL(0xd)
549#define MAIR_NORM_WB_NTR_RA ULL(0xe)
550#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
551
552#define MAIR_NORM_OUTER_SHIFT 4
553
554#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
555
Achin Gupta4f6ad662013-10-25 09:08:21 +0100556#endif /* __ARCH_H__ */