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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01008#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010010#include <auth_mod.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010011#include <bl1.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010012#include <bl_common.h>
Antonio Nino Diaze3962d02017-02-16 16:17:19 +000013#include <console.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010014#include <debug.h>
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000015#include <errata_report.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010016#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010017#include <platform_def.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010018#include <smcc_helpers.h>
Soby Mathewc53ac5e2016-07-20 14:38:36 +010019#include <utils.h>
Dan Handleybcd60ba2014-04-17 18:53:42 +010020#include "bl1_private.h"
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010021#include <uuid.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010022
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010023/* BL1 Service UUID */
24DEFINE_SVC_UUID(bl1_svc_uid,
25 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
26 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
27
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010028
Yatharth Kochara65be2f2015-10-09 18:06:13 +010029static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010030
Sandrine Bailleux467d0572014-06-24 14:02:34 +010031/*******************************************************************************
32 * The next function has a weak definition. Platform specific code can override
33 * it if it wishes to.
34 ******************************************************************************/
35#pragma weak bl1_init_bl2_mem_layout
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010036
37/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010038 * Function that takes a memory layout into which BL2 has been loaded and
39 * populates a new memory layout for BL2 that ensures that BL1's data sections
40 * resident in secure RAM are not visible to BL2.
41 ******************************************************************************/
42void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
43 meminfo_t *bl2_mem_layout)
44{
Sandrine Bailleux467d0572014-06-24 14:02:34 +010045
46 assert(bl1_mem_layout != NULL);
47 assert(bl2_mem_layout != NULL);
48
Yatharth Kochar51f76f62016-09-12 16:10:33 +010049#if LOAD_IMAGE_V2
50 /*
51 * Remove BL1 RW data from the scope of memory visible to BL2.
52 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
53 */
54 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
55 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
56 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
57#else
Sandrine Bailleux467d0572014-06-24 14:02:34 +010058 /* Check that BL1's memory is lying outside of the free memory */
59 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
Yatharth Kochara65be2f2015-10-09 18:06:13 +010060 (BL1_RAM_BASE >= bl1_mem_layout->free_base +
61 bl1_mem_layout->free_size));
Sandrine Bailleux467d0572014-06-24 14:02:34 +010062
63 /* Remove BL1 RW data from the scope of memory visible to BL2 */
64 *bl2_mem_layout = *bl1_mem_layout;
65 reserve_mem(&bl2_mem_layout->total_base,
66 &bl2_mem_layout->total_size,
67 BL1_RAM_BASE,
Yatharth Kochar51f76f62016-09-12 16:10:33 +010068 BL1_RAM_LIMIT - BL1_RAM_BASE);
69#endif /* LOAD_IMAGE_V2 */
Sandrine Bailleux467d0572014-06-24 14:02:34 +010070
71 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
72}
73
74/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010075 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +010076 * It also queries the platform to load and run next BL image. Only called
77 * by the primary cpu after a cold boot.
78 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +010079void bl1_main(void)
80{
Yatharth Kochara65be2f2015-10-09 18:06:13 +010081 unsigned int image_id;
82
Dan Handley91b624e2014-07-29 17:14:00 +010083 /* Announce our arrival */
84 NOTICE(FIRMWARE_WELCOME_STR);
85 NOTICE("BL1: %s\n", version_string);
86 NOTICE("BL1: %s\n", build_message);
87
Yatharth Kochar5d361212016-06-28 17:07:09 +010088 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
89 (void *)BL1_RAM_LIMIT);
Dan Handley91b624e2014-07-29 17:14:00 +010090
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000091 print_errata_status();
Achin Gupta4f6ad662013-10-25 09:08:21 +010092
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +000093#if ENABLE_ASSERTIONS
Yatharth Kochar5d361212016-06-28 17:07:09 +010094 u_register_t val;
Achin Gupta4f6ad662013-10-25 09:08:21 +010095 /*
96 * Ensure that MMU/Caches and coherency are turned on
97 */
Yatharth Kochar5d361212016-06-28 17:07:09 +010098#ifdef AARCH32
99 val = read_sctlr();
100#else
Dan Handley0cdebbd2015-03-30 17:15:16 +0100101 val = read_sctlr_el3();
Yatharth Kochar5d361212016-06-28 17:07:09 +0100102#endif
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100103 assert(val & SCTLR_M_BIT);
104 assert(val & SCTLR_C_BIT);
105 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100106 /*
107 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
108 * provided platform value
109 */
110 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
111 /*
112 * If CWG is zero, then no CWG information is available but we can
113 * at least check the platform value is less than the architectural
114 * maximum.
115 */
116 if (val != 0)
117 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
118 else
119 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +0000120#endif /* ENABLE_ASSERTIONS */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121
122 /* Perform remaining generic architectural setup from EL3 */
123 bl1_arch_setup();
124
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100125#if TRUSTED_BOARD_BOOT
126 /* Initialize authentication module */
127 auth_mod_init();
128#endif /* TRUSTED_BOARD_BOOT */
129
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130 /* Perform platform setup in BL1. */
131 bl1_platform_setup();
132
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100133 /* Get the image id of next image to load and run. */
134 image_id = bl1_plat_get_next_image_id();
135
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100136 /*
137 * We currently interpret any image id other than
138 * BL2_IMAGE_ID as the start of firmware update.
139 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100140 if (image_id == BL2_IMAGE_ID)
141 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100142 else
143 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100144
145 bl1_prepare_next_image(image_id);
Antonio Nino Diaze3962d02017-02-16 16:17:19 +0000146
147 console_flush();
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100148}
149
150/*******************************************************************************
151 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
152 * Called by the primary cpu after a cold boot.
153 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
154 * loader etc.
155 ******************************************************************************/
156void bl1_load_bl2(void)
157{
158 image_desc_t *image_desc;
159 image_info_t *image_info;
160 entry_point_info_t *ep_info;
161 meminfo_t *bl1_tzram_layout;
162 meminfo_t *bl2_tzram_layout;
163 int err;
164
165 /* Get the image descriptor */
166 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
167 assert(image_desc);
168
169 /* Get the image info */
170 image_info = &image_desc->image_info;
171
172 /* Get the entry point info */
173 ep_info = &image_desc->ep_info;
Vikram Kanigirida567432014-04-15 18:08:08 +0100174
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100175 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000176 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100177
Juan Castillo3a66aca2015-04-13 17:36:19 +0100178 INFO("BL1: Loading BL2\n");
179
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100180#if LOAD_IMAGE_V2
181 err = load_auth_image(BL2_IMAGE_ID, image_info);
182#else
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100183 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100184 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100185 BL2_IMAGE_ID,
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100186 image_info->image_base,
187 image_info,
188 ep_info);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100189
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100190#endif /* LOAD_IMAGE_V2 */
191
Vikram Kanigirida567432014-04-15 18:08:08 +0100192 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100193 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100194 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100195 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000196
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197 /*
198 * Create a new layout of memory for BL2 as seen by BL1 i.e.
199 * tell it the amount of total and free memory available.
200 * This layout is created at the first free address visible
201 * to BL2. BL2 will read the memory layout before using its
202 * memory for other purposes.
203 */
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100204#if LOAD_IMAGE_V2
205 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
206#else
Dan Handleye2712bc2014-04-10 15:37:22 +0100207 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100208#endif /* LOAD_IMAGE_V2 */
209
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100210 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211
Yatharth Kochar5d361212016-06-28 17:07:09 +0100212 ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100213 NOTICE("BL1: Booting BL2\n");
Yatharth Kochar5d361212016-06-28 17:07:09 +0100214 VERBOSE("BL1: BL2 memory layout address = %p\n",
215 (void *) bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216}
217
218/*******************************************************************************
Yatharth Kochar5d361212016-06-28 17:07:09 +0100219 * Function called just before handing over to the next BL to inform the user
220 * about the boot progress. In debug mode, also print details about the BL
221 * image's execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222 ******************************************************************************/
Yatharth Kochar5d361212016-06-28 17:07:09 +0100223void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224{
Yatharth Kochar5d361212016-06-28 17:07:09 +0100225#ifdef AARCH32
226 NOTICE("BL1: Booting BL32\n");
227#else
Juan Castillo7d199412015-12-14 09:35:25 +0000228 NOTICE("BL1: Booting BL31\n");
Yatharth Kochar5d361212016-06-28 17:07:09 +0100229#endif /* AARCH32 */
230 print_entry_point_info(bl_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100231}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000232
233#if SPIN_ON_BL1_EXIT
234void print_debug_loop_message(void)
235{
236 NOTICE("BL1: Debug loop, spinning forever\n");
237 NOTICE("BL1: Please connect the debugger to continue\n");
238}
239#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100240
241/*******************************************************************************
242 * Top level handler for servicing BL1 SMCs.
243 ******************************************************************************/
244register_t bl1_smc_handler(unsigned int smc_fid,
245 register_t x1,
246 register_t x2,
247 register_t x3,
248 register_t x4,
249 void *cookie,
250 void *handle,
251 unsigned int flags)
252{
253
254#if TRUSTED_BOARD_BOOT
255 /*
256 * Dispatch FWU calls to FWU SMC handler and return its return
257 * value
258 */
259 if (is_fwu_fid(smc_fid)) {
260 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
261 handle, flags);
262 }
263#endif
264
265 switch (smc_fid) {
266 case BL1_SMC_CALL_COUNT:
267 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
268
269 case BL1_SMC_UID:
270 SMC_UUID_RET(handle, bl1_svc_uid);
271
272 case BL1_SMC_VERSION:
273 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
274
275 default:
276 break;
277 }
278
279 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
280 SMC_RET1(handle, SMC_UNK);
281}