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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000034 .globl bl1_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010035
36
Achin Gupta4f6ad662013-10-25 09:08:21 +010037 /* -----------------------------------------------------
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000038 * bl1_entrypoint() is the entry point into the trusted
Achin Gupta4f6ad662013-10-25 09:08:21 +010039 * firmware code when a cpu is released from warm or
40 * cold reset.
41 * -----------------------------------------------------
42 */
43
Andrew Thoelke38bde412014-03-18 13:46:55 +000044func bl1_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 /* ---------------------------------------------
Andrew Thoelkef994ffb2014-04-24 15:33:24 +010046 * Set the CPU endianness before doing anything
Achin Gupta9f098352014-07-18 18:38:28 +010047 * that might involve memory reads or writes.
Andrew Thoelkef994ffb2014-04-24 15:33:24 +010048 * ---------------------------------------------
49 */
50 mrs x0, sctlr_el3
51 bic x0, x0, #SCTLR_EE_BIT
52 msr sctlr_el3, x0
53 isb
54
55 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010056 * Perform any processor specific actions upon
57 * reset e.g. cache, tlb invalidations etc.
58 * ---------------------------------------------
59 */
Soby Mathewc704cbc2014-08-14 11:33:56 +010060 bl reset_handler
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Achin Gupta9f098352014-07-18 18:38:28 +010062 /* ---------------------------------------------
63 * Enable the instruction cache, stack pointer
64 * and data access alignment checks
65 * ---------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +010066 */
Achin Gupta9f098352014-07-18 18:38:28 +010067 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Vikram Kanigiri96377452014-04-24 11:02:16 +010068 mrs x0, sctlr_el3
Achin Gupta9f098352014-07-18 18:38:28 +010069 orr x0, x0, x1
Vikram Kanigiri96377452014-04-24 11:02:16 +010070 msr sctlr_el3, x0
71 isb
72
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000073 /* ---------------------------------------------
74 * Set the exception vector to something sane.
75 * ---------------------------------------------
76 */
Sandrine Bailleux4d052752014-03-24 10:24:08 +000077 adr x0, bl1_exceptions
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000078 msr vbar_el3, x0
Achin Guptaed1744e2014-08-04 23:13:10 +010079 isb
80
81 /* ---------------------------------------------
82 * Enable the SError interrupt now that the
83 * exception vectors have been setup.
84 * ---------------------------------------------
85 */
86 msr daifclr, #DAIF_ABT_BIT
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000087
Harry Liebel4f603682014-01-14 18:11:48 +000088 /* ---------------------------------------------------------------------
89 * The initial state of the Architectural feature trap register
90 * (CPTR_EL3) is unknown and it must be set to a known state. All
91 * feature traps are disabled. Some bits in this register are marked as
92 * Reserved and should not be modified.
93 *
94 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
95 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
96 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
97 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
98 * access to trace functionality is not supported, this bit is RES0.
99 * CPTR_EL3.TFP: This causes instructions that access the registers
100 * associated with Floating Point and Advanced SIMD execution to trap
101 * to EL3 when executed from any exception level, unless trapped to EL1
102 * or EL2.
103 * ---------------------------------------------------------------------
104 */
105 mrs x0, cptr_el3
106 bic w0, w0, #TCPAC_BIT
107 bic w0, w0, #TTA_BIT
108 bic w0, w0, #TFP_BIT
109 msr cptr_el3, x0
110
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100111 /* -------------------------------------------------------
112 * Will not return from this macro if it is a warm boot.
113 * -------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114 */
Vikram Kanigiri96377452014-04-24 11:02:16 +0100115 wait_for_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
Vikram Kanigiri96377452014-04-24 11:02:16 +0100117 bl platform_mem_init
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000120 * Init C runtime environment.
121 * - Zero-initialise the NOBITS sections.
122 * There are 2 of them:
123 * - the .bss section;
124 * - the coherent memory section.
125 * - Copy the data section from BL1 image
126 * (stored in ROM) to the correct location
127 * in RAM.
128 * ---------------------------------------------
129 */
130 ldr x0, =__BSS_START__
131 ldr x1, =__BSS_SIZE__
132 bl zeromem16
133
134 ldr x0, =__COHERENT_RAM_START__
135 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
136 bl zeromem16
137
138 ldr x0, =__DATA_RAM_START__
139 ldr x1, =__DATA_ROM_START__
140 ldr x2, =__DATA_SIZE__
141 bl memcpy16
142
Achin Guptaf4a97092014-06-25 19:26:22 +0100143 /* --------------------------------------------
144 * Allocate a stack whose memory will be marked
145 * as Normal-IS-WBWA when the MMU is enabled.
146 * There is no risk of reading stale stack
147 * memory after enabling the MMU as only the
148 * primary cpu is running at the moment.
149 * --------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +0100150 */
151 mrs x0, mpidr_el1
Achin Guptaf4a97092014-06-25 19:26:22 +0100152 bl platform_set_stack
Vikram Kanigiri96377452014-04-24 11:02:16 +0100153
154 /* ---------------------------------------------
155 * Architectural init. can be generic e.g.
156 * enabling stack alignment and platform spec-
157 * ific e.g. MMU & page table setup as per the
158 * platform memory map. Perform the latter here
159 * and the former in bl1_main.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160 * ---------------------------------------------
161 */
Vikram Kanigiri96377452014-04-24 11:02:16 +0100162 bl bl1_early_platform_setup
163 bl bl1_plat_arch_setup
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164
Vikram Kanigiri96377452014-04-24 11:02:16 +0100165 /* --------------------------------------------------
166 * Initialize platform and jump to our c-entry point
167 * for this type of reset. Panic if it returns
168 * --------------------------------------------------
169 */
170 bl bl1_main
171panic:
172 b panic