Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 1dcffa9 | 2016-01-08 17:48:42 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <bl31.h> |
| 35 | #include <bl_common.h> |
| 36 | #include <console.h> |
| 37 | #include <cortex_a57.h> |
| 38 | #include <cortex_a53.h> |
| 39 | #include <debug.h> |
Varun Wadekar | baf903e | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 40 | #include <denver.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 41 | #include <errno.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 42 | #include <memctrl.h> |
| 43 | #include <mmio.h> |
| 44 | #include <platform.h> |
| 45 | #include <platform_def.h> |
| 46 | #include <stddef.h> |
Varun Wadekar | 0dc9181 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 47 | #include <tegra_def.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 48 | #include <tegra_private.h> |
| 49 | |
| 50 | /******************************************************************************* |
| 51 | * Declarations of linker defined symbols which will help us find the layout |
| 52 | * of trusted SRAM |
| 53 | ******************************************************************************/ |
| 54 | extern unsigned long __RO_START__; |
| 55 | extern unsigned long __RO_END__; |
| 56 | extern unsigned long __BL31_END__; |
| 57 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 58 | extern uint64_t tegra_bl31_phys_base; |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 59 | extern uint64_t tegra_console_base; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 60 | |
| 61 | /* |
| 62 | * The next 3 constants identify the extents of the code, RO data region and the |
| 63 | * limit of the BL3-1 image. These addresses are used by the MMU setup code and |
| 64 | * therefore they must be page-aligned. It is the responsibility of the linker |
| 65 | * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols |
| 66 | * refer to page-aligned addresses. |
| 67 | */ |
| 68 | #define BL31_RO_BASE (unsigned long)(&__RO_START__) |
| 69 | #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) |
| 70 | #define BL31_END (unsigned long)(&__BL31_END__) |
| 71 | |
Varun Wadekar | 52a1598 | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 72 | static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 73 | static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { |
Varun Wadekar | c8bfe2e | 2015-07-31 10:03:01 +0530 | [diff] [blame] | 74 | .tzdram_size = (uint64_t)TZDRAM_SIZE |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | /******************************************************************************* |
| 78 | * This variable holds the non-secure image entry address |
| 79 | ******************************************************************************/ |
| 80 | extern uint64_t ns_image_entrypoint; |
| 81 | |
| 82 | /******************************************************************************* |
Varun Wadekar | 3f0a8ad | 2016-03-28 15:56:47 -0700 | [diff] [blame] | 83 | * The following platform setup functions are weakly defined. They |
| 84 | * provide typical implementations that will be overridden by a SoC. |
| 85 | ******************************************************************************/ |
| 86 | #pragma weak plat_early_platform_setup |
| 87 | |
| 88 | void plat_early_platform_setup(void) |
| 89 | { |
| 90 | ; /* do nothing */ |
| 91 | } |
| 92 | |
| 93 | /******************************************************************************* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 94 | * Return a pointer to the 'entry_point_info' structure of the next image for |
| 95 | * security state specified. BL33 corresponds to the non-secure image type |
| 96 | * while BL32 corresponds to the secure image type. |
| 97 | ******************************************************************************/ |
| 98 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 99 | { |
| 100 | if (type == NON_SECURE) |
| 101 | return &bl33_image_ep_info; |
| 102 | |
Varun Wadekar | 52a1598 | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 103 | if (type == SECURE) |
| 104 | return &bl32_image_ep_info; |
| 105 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 106 | return NULL; |
| 107 | } |
| 108 | |
| 109 | /******************************************************************************* |
| 110 | * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image |
| 111 | * passes this platform specific information. |
| 112 | ******************************************************************************/ |
| 113 | plat_params_from_bl2_t *bl31_get_plat_params(void) |
| 114 | { |
| 115 | return &plat_bl31_params_from_bl2; |
| 116 | } |
| 117 | |
| 118 | /******************************************************************************* |
| 119 | * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image |
| 120 | * info. |
| 121 | ******************************************************************************/ |
| 122 | void bl31_early_platform_setup(bl31_params_t *from_bl2, |
| 123 | void *plat_params_from_bl2) |
| 124 | { |
| 125 | plat_params_from_bl2_t *plat_params = |
| 126 | (plat_params_from_bl2_t *)plat_params_from_bl2; |
Varun Wadekar | baf903e | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 127 | #if DEBUG |
| 128 | int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
| 129 | #endif |
Varun Wadekar | baf903e | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 130 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 131 | /* |
Varun Wadekar | 52a1598 | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 132 | * Copy BL3-3, BL3-2 entry point information. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 133 | * They are stored in Secure RAM, in BL2's address space. |
| 134 | */ |
Varun Wadekar | 6bb6246 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 135 | assert(from_bl2->bl33_ep_info); |
| 136 | bl33_image_ep_info = *from_bl2->bl33_ep_info; |
Varun Wadekar | baf903e | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 137 | |
| 138 | if (from_bl2->bl32_ep_info) |
| 139 | bl32_image_ep_info = *from_bl2->bl32_ep_info; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 140 | |
| 141 | /* |
Varun Wadekar | 6bb6246 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 142 | * Parse platform specific parameters - TZDRAM aperture base and size |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 143 | */ |
Varun Wadekar | 6bb6246 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 144 | assert(plat_params); |
| 145 | plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; |
| 146 | plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 147 | plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; |
| 148 | |
| 149 | /* |
Varun Wadekar | 1ec441e | 2016-03-24 15:34:24 -0700 | [diff] [blame] | 150 | * It is very important that we run either from TZDRAM or TZSRAM base. |
| 151 | * Add an explicit check here. |
| 152 | */ |
| 153 | if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && |
| 154 | (TEGRA_TZRAM_BASE != BL31_BASE)) |
| 155 | panic(); |
| 156 | |
| 157 | /* |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 158 | * Get the base address of the UART controller to be used for the |
| 159 | * console |
| 160 | */ |
| 161 | assert(plat_params->uart_id); |
| 162 | tegra_console_base = plat_get_console_from_id(plat_params->uart_id); |
| 163 | |
| 164 | /* |
| 165 | * Configure the UART port to be used as the console |
| 166 | */ |
| 167 | assert(tegra_console_base); |
| 168 | console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, |
| 169 | TEGRA_CONSOLE_BAUDRATE); |
| 170 | |
| 171 | /* Initialise crash console */ |
| 172 | plat_crash_console_init(); |
| 173 | |
Varun Wadekar | 3f0a8ad | 2016-03-28 15:56:47 -0700 | [diff] [blame] | 174 | /* Early platform setup for Tegra SoCs */ |
| 175 | plat_early_platform_setup(); |
| 176 | |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 177 | INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? |
| 178 | "Denver" : "ARM", read_mpidr()); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /******************************************************************************* |
| 182 | * Initialize the gic, configure the SCR. |
| 183 | ******************************************************************************/ |
| 184 | void bl31_platform_setup(void) |
| 185 | { |
| 186 | uint32_t tmp_reg; |
| 187 | |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 188 | /* Initialize the gic cpu and distributor interfaces */ |
| 189 | plat_gic_setup(); |
| 190 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 191 | /* |
Varun Wadekar | bc74fec | 2015-07-16 15:47:03 +0530 | [diff] [blame] | 192 | * Initialize delay timer |
| 193 | */ |
| 194 | tegra_delay_timer_init(); |
| 195 | |
| 196 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 197 | * Setup secondary CPU POR infrastructure. |
| 198 | */ |
| 199 | plat_secondary_setup(); |
| 200 | |
| 201 | /* |
| 202 | * Initial Memory Controller configuration. |
| 203 | */ |
| 204 | tegra_memctrl_setup(); |
| 205 | |
| 206 | /* |
| 207 | * Do initial security configuration to allow DRAM/device access. |
| 208 | */ |
Varun Wadekar | 6bb6246 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 209 | tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 210 | plat_bl31_params_from_bl2.tzdram_size); |
| 211 | |
Varun Wadekar | 0dc9181 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 212 | /* |
| 213 | * Set up the TZRAM memory aperture to allow only secure world |
| 214 | * access |
| 215 | */ |
| 216 | tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); |
| 217 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 218 | /* Set the next EL to be AArch64 */ |
| 219 | tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; |
| 220 | write_scr(tmp_reg); |
| 221 | |
Varun Wadekar | baf903e | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 222 | INFO("BL3-1: Tegra platform setup complete\n"); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 223 | } |
| 224 | |
| 225 | /******************************************************************************* |
Varun Wadekar | 1dcffa9 | 2016-01-08 17:48:42 -0800 | [diff] [blame] | 226 | * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit |
| 227 | ******************************************************************************/ |
| 228 | void bl31_plat_runtime_setup(void) |
| 229 | { |
| 230 | /* Initialize the runtime console */ |
| 231 | console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, |
| 232 | TEGRA_CONSOLE_BAUDRATE); |
| 233 | } |
| 234 | |
| 235 | /******************************************************************************* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 236 | * Perform the very early platform specific architectural setup here. At the |
| 237 | * moment this only intializes the mmu in a quick and dirty way. |
| 238 | ******************************************************************************/ |
| 239 | void bl31_plat_arch_setup(void) |
| 240 | { |
| 241 | unsigned long bl31_base_pa = tegra_bl31_phys_base; |
| 242 | unsigned long total_base = bl31_base_pa; |
Varun Wadekar | e1eaf8e | 2015-08-11 14:20:14 +0530 | [diff] [blame] | 243 | unsigned long total_size = BL32_BASE - BL31_RO_BASE; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 244 | unsigned long ro_start = bl31_base_pa; |
| 245 | unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 246 | const mmap_region_t *plat_mmio_map = NULL; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 247 | #if USE_COHERENT_MEM |
Varun Wadekar | 207cc73 | 2015-07-08 12:57:50 +0530 | [diff] [blame] | 248 | unsigned long coh_start, coh_size; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 249 | #endif |
Varun Wadekar | d151363 | 2016-03-18 13:01:12 -0700 | [diff] [blame] | 250 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 251 | |
| 252 | /* add memory regions */ |
| 253 | mmap_add_region(total_base, total_base, |
| 254 | total_size, |
| 255 | MT_MEMORY | MT_RW | MT_SECURE); |
| 256 | mmap_add_region(ro_start, ro_start, |
| 257 | ro_size, |
| 258 | MT_MEMORY | MT_RO | MT_SECURE); |
Varun Wadekar | 207cc73 | 2015-07-08 12:57:50 +0530 | [diff] [blame] | 259 | |
Varun Wadekar | d151363 | 2016-03-18 13:01:12 -0700 | [diff] [blame] | 260 | /* map TZDRAM used by BL31 as coherent memory */ |
| 261 | if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { |
| 262 | mmap_add_region(params_from_bl2->tzdram_base, |
| 263 | params_from_bl2->tzdram_base, |
| 264 | BL31_SIZE, |
| 265 | MT_DEVICE | MT_RW | MT_SECURE); |
| 266 | } |
| 267 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 268 | #if USE_COHERENT_MEM |
Masahiro Yamada | 0fac5af | 2016-12-28 16:11:41 +0900 | [diff] [blame] | 269 | coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); |
| 270 | coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; |
Varun Wadekar | 207cc73 | 2015-07-08 12:57:50 +0530 | [diff] [blame] | 271 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 272 | mmap_add_region(coh_start, coh_start, |
| 273 | coh_size, |
| 274 | MT_DEVICE | MT_RW | MT_SECURE); |
| 275 | #endif |
| 276 | |
| 277 | /* add MMIO space */ |
| 278 | plat_mmio_map = plat_get_mmio_map(); |
| 279 | if (plat_mmio_map) |
| 280 | mmap_add(plat_mmio_map); |
| 281 | else |
| 282 | WARN("MMIO map not available\n"); |
| 283 | |
| 284 | /* set up translation tables */ |
| 285 | init_xlat_tables(); |
| 286 | |
| 287 | /* enable the MMU */ |
| 288 | enable_mmu_el3(0); |
Varun Wadekar | baf903e | 2015-09-22 15:00:06 +0530 | [diff] [blame] | 289 | |
| 290 | INFO("BL3-1: Tegra: MMU enabled\n"); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 291 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 292 | |
| 293 | /******************************************************************************* |
| 294 | * Check if the given NS DRAM range is valid |
| 295 | ******************************************************************************/ |
| 296 | int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) |
| 297 | { |
| 298 | uint64_t end = base + size_in_bytes - 1; |
| 299 | |
| 300 | /* |
| 301 | * Check if the NS DRAM address is valid |
| 302 | */ |
| 303 | if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || |
| 304 | (base >= end)) { |
| 305 | ERROR("NS address is out-of-bounds!\n"); |
| 306 | return -EFAULT; |
| 307 | } |
| 308 | |
| 309 | /* |
| 310 | * TZDRAM aperture contains the BL31 and BL32 images, so we need |
| 311 | * to check if the NS DRAM range overlaps the TZDRAM aperture. |
| 312 | */ |
| 313 | if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { |
| 314 | ERROR("NS address overlaps TZDRAM!\n"); |
| 315 | return -ENOTSUP; |
| 316 | } |
| 317 | |
| 318 | /* valid NS address */ |
| 319 | return 0; |
| 320 | } |