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Sandrine Bailleux27866d82013-10-25 15:33:39 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux27866d82013-10-25 15:33:39 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __GIC_V2_H__
32#define __GIC_V2_H__
33
Dan Handley930ee2e2014-04-17 17:48:52 +010034
35#define GIC400_NUM_SPIS 480
36#define MAX_PPIS 14
37#define MAX_SGIS 16
38
Dan Handleyfb42b122014-06-20 09:43:15 +010039#define MIN_SGI_ID 0
40#define MIN_PPI_ID 16
41#define MIN_SPI_ID 32
42
Dan Handley930ee2e2014-04-17 17:48:52 +010043#define GRP0 0
44#define GRP1 1
45#define GIC_PRI_MASK 0xff
46#define GIC_HIGHEST_SEC_PRIORITY 0
47#define GIC_LOWEST_SEC_PRIORITY 127
48#define GIC_HIGHEST_NS_PRIORITY 128
49#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */
Achin Gupta02d36282014-05-04 19:02:52 +010050#define GIC_SPURIOUS_INTERRUPT 1023
Juan Castillo82312952014-10-20 12:27:28 +010051#define GIC_TARGET_CPU_MASK 0xff
Dan Handley930ee2e2014-04-17 17:48:52 +010052
53#define ENABLE_GRP0 (1 << 0)
54#define ENABLE_GRP1 (1 << 1)
55
56/* Distributor interface definitions */
57#define GICD_CTLR 0x0
58#define GICD_TYPER 0x4
59#define GICD_IGROUPR 0x80
60#define GICD_ISENABLER 0x100
61#define GICD_ICENABLER 0x180
62#define GICD_ISPENDR 0x200
63#define GICD_ICPENDR 0x280
64#define GICD_ISACTIVER 0x300
65#define GICD_ICACTIVER 0x380
66#define GICD_IPRIORITYR 0x400
67#define GICD_ITARGETSR 0x800
68#define GICD_ICFGR 0xC00
69#define GICD_SGIR 0xF00
70#define GICD_CPENDSGIR 0xF10
71#define GICD_SPENDSGIR 0xF20
72
73#define IGROUPR_SHIFT 5
74#define ISENABLER_SHIFT 5
75#define ICENABLER_SHIFT ISENABLER_SHIFT
76#define ISPENDR_SHIFT 5
77#define ICPENDR_SHIFT ISPENDR_SHIFT
78#define ISACTIVER_SHIFT 5
79#define ICACTIVER_SHIFT ISACTIVER_SHIFT
80#define IPRIORITYR_SHIFT 2
81#define ITARGETSR_SHIFT 2
82#define ICFGR_SHIFT 4
83#define CPENDSGIR_SHIFT 2
84#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
85
86/* GICD_TYPER bit definitions */
87#define IT_LINES_NO_MASK 0x1f
88
89/* Physical CPU Interface registers */
90#define GICC_CTLR 0x0
91#define GICC_PMR 0x4
92#define GICC_BPR 0x8
93#define GICC_IAR 0xC
94#define GICC_EOIR 0x10
95#define GICC_RPR 0x14
96#define GICC_HPPIR 0x18
Achin Gupta02d36282014-05-04 19:02:52 +010097#define GICC_AHPPIR 0x28
Dan Handley930ee2e2014-04-17 17:48:52 +010098#define GICC_IIDR 0xFC
99#define GICC_DIR 0x1000
100#define GICC_PRIODROP GICC_EOIR
101
Achin Gupta966b9522015-05-18 10:56:47 +0100102/* Common CPU Interface definitions */
103#define INT_ID_MASK 0x3ff
104
Dan Handley930ee2e2014-04-17 17:48:52 +0100105/* GICC_CTLR bit definitions */
106#define EOI_MODE_NS (1 << 10)
107#define EOI_MODE_S (1 << 9)
108#define IRQ_BYP_DIS_GRP1 (1 << 8)
109#define FIQ_BYP_DIS_GRP1 (1 << 7)
110#define IRQ_BYP_DIS_GRP0 (1 << 6)
111#define FIQ_BYP_DIS_GRP0 (1 << 5)
112#define CBPR (1 << 4)
113#define FIQ_EN (1 << 3)
114#define ACK_CTL (1 << 2)
115
116/* GICC_IIDR bit masks and shifts */
117#define GICC_IIDR_PID_SHIFT 20
118#define GICC_IIDR_ARCH_SHIFT 16
119#define GICC_IIDR_REV_SHIFT 12
120#define GICC_IIDR_IMP_SHIFT 0
121
122#define GICC_IIDR_PID_MASK 0xfff
123#define GICC_IIDR_ARCH_MASK 0xf
124#define GICC_IIDR_REV_MASK 0xf
125#define GICC_IIDR_IMP_MASK 0xfff
126
127/* HYP view virtual CPU Interface registers */
128#define GICH_CTL 0x0
129#define GICH_VTR 0x4
130#define GICH_ELRSR0 0x30
131#define GICH_ELRSR1 0x34
132#define GICH_APR0 0xF0
133#define GICH_LR_BASE 0x100
134
135/* Virtual CPU Interface registers */
136#define GICV_CTL 0x0
137#define GICV_PRIMASK 0x4
138#define GICV_BP 0x8
139#define GICV_INTACK 0xC
140#define GICV_EOI 0x10
141#define GICV_RUNNINGPRI 0x14
142#define GICV_HIGHESTPEND 0x18
143#define GICV_DEACTIVATE 0x1000
144
145#ifndef __ASSEMBLY__
146
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100147#include <mmio.h>
Juan Castillo7f1f0622014-09-09 09:49:23 +0100148#include <stdint.h>
Dan Handley930ee2e2014-04-17 17:48:52 +0100149
150/*******************************************************************************
151 * GIC Distributor function prototypes
152 ******************************************************************************/
153
Juan Castillo7f1f0622014-09-09 09:49:23 +0100154unsigned int gicd_read_igroupr(uintptr_t, unsigned int);
155unsigned int gicd_read_isenabler(uintptr_t, unsigned int);
156unsigned int gicd_read_icenabler(uintptr_t, unsigned int);
157unsigned int gicd_read_ispendr(uintptr_t, unsigned int);
158unsigned int gicd_read_icpendr(uintptr_t, unsigned int);
159unsigned int gicd_read_isactiver(uintptr_t, unsigned int);
160unsigned int gicd_read_icactiver(uintptr_t, unsigned int);
161unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int);
162unsigned int gicd_read_itargetsr(uintptr_t, unsigned int);
163unsigned int gicd_read_icfgr(uintptr_t, unsigned int);
164unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int);
165unsigned int gicd_read_spendsgir(uintptr_t, unsigned int);
166void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int);
167void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int);
168void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int);
169void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int);
170void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int);
171void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int);
172void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int);
173void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int);
174void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int);
175void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int);
176void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int);
177void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int);
178unsigned int gicd_get_igroupr(uintptr_t, unsigned int);
179void gicd_set_igroupr(uintptr_t, unsigned int);
180void gicd_clr_igroupr(uintptr_t, unsigned int);
181void gicd_set_isenabler(uintptr_t, unsigned int);
182void gicd_set_icenabler(uintptr_t, unsigned int);
183void gicd_set_ispendr(uintptr_t, unsigned int);
184void gicd_set_icpendr(uintptr_t, unsigned int);
185void gicd_set_isactiver(uintptr_t, unsigned int);
186void gicd_set_icactiver(uintptr_t, unsigned int);
187void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int);
188void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int);
Dan Handley930ee2e2014-04-17 17:48:52 +0100189
190
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100191/*******************************************************************************
192 * GIC Distributor interface accessors for reading entire registers
193 ******************************************************************************/
194
Juan Castillo7f1f0622014-09-09 09:49:23 +0100195static inline unsigned int gicd_read_ctlr(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100196{
197 return mmio_read_32(base + GICD_CTLR);
198}
199
Juan Castillo7f1f0622014-09-09 09:49:23 +0100200static inline unsigned int gicd_read_typer(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100201{
202 return mmio_read_32(base + GICD_TYPER);
203}
204
Juan Castillo7f1f0622014-09-09 09:49:23 +0100205static inline unsigned int gicd_read_sgir(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100206{
207 return mmio_read_32(base + GICD_SGIR);
208}
209
210
211/*******************************************************************************
212 * GIC Distributor interface accessors for writing entire registers
213 ******************************************************************************/
214
Juan Castillo7f1f0622014-09-09 09:49:23 +0100215static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100216{
217 mmio_write_32(base + GICD_CTLR, val);
218}
219
Juan Castillo7f1f0622014-09-09 09:49:23 +0100220static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100221{
222 mmio_write_32(base + GICD_SGIR, val);
223}
224
225
226/*******************************************************************************
227 * GIC CPU interface accessors for reading entire registers
228 ******************************************************************************/
229
Juan Castillo7f1f0622014-09-09 09:49:23 +0100230static inline unsigned int gicc_read_ctlr(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100231{
232 return mmio_read_32(base + GICC_CTLR);
233}
234
Juan Castillo7f1f0622014-09-09 09:49:23 +0100235static inline unsigned int gicc_read_pmr(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100236{
237 return mmio_read_32(base + GICC_PMR);
238}
239
Juan Castillo7f1f0622014-09-09 09:49:23 +0100240static inline unsigned int gicc_read_BPR(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100241{
242 return mmio_read_32(base + GICC_BPR);
243}
244
Juan Castillo7f1f0622014-09-09 09:49:23 +0100245static inline unsigned int gicc_read_IAR(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100246{
247 return mmio_read_32(base + GICC_IAR);
248}
249
Juan Castillo7f1f0622014-09-09 09:49:23 +0100250static inline unsigned int gicc_read_EOIR(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100251{
252 return mmio_read_32(base + GICC_EOIR);
253}
254
Juan Castillo7f1f0622014-09-09 09:49:23 +0100255static inline unsigned int gicc_read_hppir(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100256{
257 return mmio_read_32(base + GICC_HPPIR);
258}
259
Juan Castillo7f1f0622014-09-09 09:49:23 +0100260static inline unsigned int gicc_read_ahppir(uintptr_t base)
Achin Gupta02d36282014-05-04 19:02:52 +0100261{
262 return mmio_read_32(base + GICC_AHPPIR);
263}
264
Juan Castillo7f1f0622014-09-09 09:49:23 +0100265static inline unsigned int gicc_read_dir(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100266{
267 return mmio_read_32(base + GICC_DIR);
268}
269
Juan Castillo7f1f0622014-09-09 09:49:23 +0100270static inline unsigned int gicc_read_iidr(uintptr_t base)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100271{
272 return mmio_read_32(base + GICC_IIDR);
273}
274
275
276/*******************************************************************************
277 * GIC CPU interface accessors for writing entire registers
278 ******************************************************************************/
279
Juan Castillo7f1f0622014-09-09 09:49:23 +0100280static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100281{
282 mmio_write_32(base + GICC_CTLR, val);
283}
284
Juan Castillo7f1f0622014-09-09 09:49:23 +0100285static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100286{
287 mmio_write_32(base + GICC_PMR, val);
288}
289
Juan Castillo7f1f0622014-09-09 09:49:23 +0100290static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100291{
292 mmio_write_32(base + GICC_BPR, val);
293}
294
295
Juan Castillo7f1f0622014-09-09 09:49:23 +0100296static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100297{
298 mmio_write_32(base + GICC_IAR, val);
299}
300
Juan Castillo7f1f0622014-09-09 09:49:23 +0100301static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100302{
303 mmio_write_32(base + GICC_EOIR, val);
304}
305
Juan Castillo7f1f0622014-09-09 09:49:23 +0100306static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100307{
308 mmio_write_32(base + GICC_HPPIR, val);
309}
310
Juan Castillo7f1f0622014-09-09 09:49:23 +0100311static inline void gicc_write_dir(uintptr_t base, unsigned int val)
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100312{
313 mmio_write_32(base + GICC_DIR, val);
314}
315
Achin Gupta191e86e2014-05-09 10:03:15 +0100316/*******************************************************************************
317 * Prototype of function to map an interrupt type to the interrupt line used to
318 * signal it.
319 ******************************************************************************/
320uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
321
Dan Handley930ee2e2014-04-17 17:48:52 +0100322#endif /*__ASSEMBLY__*/
323
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100324#endif /* __GIC_V2_H__ */