Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 7 | #include <assert.h> |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 8 | #include <cortex_a57.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <arch_helpers.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <drivers/delay_timer.h> |
| 12 | #include <lib/mmio.h> |
| 13 | #include <lib/psci/psci.h> |
| 14 | #include <plat/common/platform.h> |
| 15 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 16 | #include <bpmp.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <flowctrl.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 18 | #include <pmc.h> |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 19 | #include <platform_def.h> |
| 20 | #include <security_engine.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 21 | #include <tegra_def.h> |
| 22 | #include <tegra_private.h> |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 23 | #include <tegra_platform.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 24 | |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 25 | /* |
| 26 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 27 | * signals: CPU reset (3:0) and Core reset (19:16). |
| 28 | */ |
| 29 | #define CPU_CMPLX_RESET_CLR 0x454 |
| 30 | #define CPU_CORE_RESET_MASK 0x10001 |
| 31 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 32 | /* Clock and Reset controller registers for system clock's settings */ |
| 33 | #define SCLK_RATE 0x30 |
| 34 | #define SCLK_BURST_POLICY 0x28 |
| 35 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 36 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 37 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 38 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 39 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 40 | psci_power_state_t *req_state) |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 41 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 42 | int state_id = psci_get_pstate_id(power_state); |
| 43 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 44 | /* Sanity check the requested state id */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 45 | switch (state_id) { |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 46 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 47 | /* |
| 48 | * Core powerdown request only for afflvl 0 |
| 49 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 50 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; |
| 51 | |
| 52 | break; |
| 53 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 54 | case PSTATE_ID_CLUSTER_IDLE: |
| 55 | case PSTATE_ID_CLUSTER_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 56 | /* |
| 57 | * Cluster powerdown/idle request only for afflvl 1 |
| 58 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 59 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 60 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 61 | |
| 62 | break; |
| 63 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 64 | case PSTATE_ID_SOC_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 65 | /* |
| 66 | * System powerdown request only for afflvl 2 |
| 67 | */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 68 | for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 69 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 70 | |
| 71 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 72 | PLAT_SYS_SUSPEND_STATE_ID; |
| 73 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 74 | break; |
| 75 | |
| 76 | default: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 77 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 78 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 79 | } |
| 80 | |
| 81 | return PSCI_E_SUCCESS; |
| 82 | } |
| 83 | |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 84 | /******************************************************************************* |
| 85 | * Platform handler to calculate the proper target power level at the |
| 86 | * specified affinity level |
| 87 | ******************************************************************************/ |
| 88 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 89 | const plat_local_state_t *states, |
| 90 | unsigned int ncpu) |
| 91 | { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 92 | plat_local_state_t target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 93 | int cpu = plat_my_core_pos(); |
| 94 | int core_pos = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 95 | uint32_t bpmp_reply, data[3]; |
| 96 | int ret; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 97 | |
| 98 | /* get the power state at this level */ |
| 99 | if (lvl == MPIDR_AFFLVL1) |
| 100 | target = *(states + core_pos); |
| 101 | if (lvl == MPIDR_AFFLVL2) |
| 102 | target = *(states + cpu); |
| 103 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 104 | if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { |
| 105 | |
| 106 | /* initialize the bpmp interface */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 107 | ret = tegra_bpmp_init(); |
| 108 | if (ret != 0U) { |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 109 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 110 | /* Cluster idle not allowed */ |
| 111 | target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 112 | } else { |
| 113 | |
| 114 | /* Cluster idle */ |
| 115 | data[0] = (uint32_t)cpu; |
| 116 | data[1] = TEGRA_PM_CC6; |
| 117 | data[2] = TEGRA_PM_SC1; |
| 118 | ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, |
| 119 | (void *)&data, (int)sizeof(data), |
| 120 | (void *)&bpmp_reply, |
| 121 | (int)sizeof(bpmp_reply)); |
| 122 | |
| 123 | /* check if cluster idle entry is allowed */ |
| 124 | if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { |
| 125 | |
| 126 | /* Cluster idle not allowed */ |
| 127 | target = PSCI_LOCAL_STATE_RUN; |
| 128 | } |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | } else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) { |
| 132 | |
| 133 | /* initialize the bpmp interface */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 134 | ret = tegra_bpmp_init(); |
| 135 | if (ret != 0U) { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 136 | |
| 137 | /* Cluster power down not allowed */ |
| 138 | target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 139 | } else { |
| 140 | |
| 141 | /* Cluster power-down */ |
| 142 | data[0] = (uint32_t)cpu; |
| 143 | data[1] = TEGRA_PM_CC7; |
| 144 | data[2] = TEGRA_PM_SC1; |
| 145 | ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, |
| 146 | (void *)&data, (int)sizeof(data), |
| 147 | (void *)&bpmp_reply, |
| 148 | (int)sizeof(bpmp_reply)); |
| 149 | |
| 150 | /* check if cluster power down is allowed */ |
| 151 | if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { |
| 152 | |
| 153 | /* Cluster power down not allowed */ |
| 154 | target = PSCI_LOCAL_STATE_RUN; |
| 155 | } |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 156 | } |
| 157 | |
| 158 | } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && |
| 159 | (target == PSTATE_ID_SOC_POWERDN)) { |
| 160 | |
| 161 | /* System Suspend */ |
| 162 | target = PSTATE_ID_SOC_POWERDN; |
| 163 | |
| 164 | } else { |
| 165 | ; /* do nothing */ |
| 166 | } |
| 167 | |
| 168 | return target; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 169 | } |
| 170 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 171 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 172 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 173 | u_register_t mpidr = read_mpidr(); |
| 174 | const plat_local_state_t *pwr_domain_state = |
| 175 | target_state->pwr_domain_state; |
| 176 | unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; |
| 177 | unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; |
| 178 | unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 179 | int ret = PSCI_E_SUCCESS; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 180 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 181 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 182 | |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 183 | assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 184 | (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 185 | assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 186 | (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); |
| 187 | |
| 188 | if (tegra_chipid_is_t210_b01()) { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 189 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 190 | /* Suspend se/se2 and pka1 */ |
| 191 | if (tegra_se_suspend() != 0) { |
| 192 | ret = PSCI_E_INTERN_FAIL; |
| 193 | } |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 194 | } |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 195 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 196 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 197 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 198 | assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 199 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 200 | /* Prepare for cluster idle */ |
| 201 | tegra_fc_cluster_idle(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 202 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 203 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 204 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 205 | assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 206 | |
| 207 | /* Prepare for cluster powerdn */ |
| 208 | tegra_fc_cluster_powerdn(mpidr); |
| 209 | |
| 210 | } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { |
| 211 | |
| 212 | /* Prepare for cpu powerdn */ |
| 213 | tegra_fc_cpu_powerdn(mpidr); |
| 214 | |
| 215 | } else { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 216 | ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, |
| 217 | stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 218 | ret = PSCI_E_NOT_SUPPORTED; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 219 | } |
| 220 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 221 | return ret; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 222 | } |
| 223 | |
Harvey Hsieh | a16d4ea | 2017-06-15 16:28:43 -0700 | [diff] [blame] | 224 | int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
| 225 | { |
| 226 | u_register_t mpidr = read_mpidr(); |
| 227 | const plat_local_state_t *pwr_domain_state = |
| 228 | target_state->pwr_domain_state; |
| 229 | unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; |
| 230 | |
| 231 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 232 | |
| 233 | if (tegra_chipid_is_t210_b01()) { |
| 234 | /* Save tzram contents */ |
| 235 | tegra_se_save_tzram(); |
| 236 | } |
| 237 | |
| 238 | /* enter system suspend */ |
| 239 | tegra_fc_soc_powerdn(mpidr); |
| 240 | } |
| 241 | |
| 242 | return PSCI_E_SUCCESS; |
| 243 | } |
| 244 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 245 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 246 | { |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 247 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 248 | uint32_t val; |
| 249 | |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 250 | /* platform parameter passed by the previous bootloader */ |
| 251 | if (plat_params->l2_ecc_parity_prot_dis != 1) { |
| 252 | /* Enable ECC Parity Protection for Cortex-A57 CPUs */ |
| 253 | val = read_l2ctlr_el1(); |
| 254 | val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; |
| 255 | write_l2ctlr_el1(val); |
| 256 | } |
| 257 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 258 | /* |
| 259 | * Check if we are exiting from SOC_POWERDN. |
| 260 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 261 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 262 | PLAT_SYS_SUSPEND_STATE_ID) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 263 | |
| 264 | /* |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 265 | * Security engine resume |
| 266 | */ |
| 267 | if (tegra_chipid_is_t210_b01()) { |
| 268 | tegra_se_resume(); |
| 269 | } |
| 270 | |
| 271 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 272 | * Lock scratch registers which hold the CPU vectors |
| 273 | */ |
| 274 | tegra_pmc_lock_cpu_vectors(); |
| 275 | |
| 276 | /* |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 277 | * Enable WRAP to INCR burst type conversions for |
| 278 | * incoming requests on the AXI slave ports. |
| 279 | */ |
| 280 | val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); |
| 281 | val &= ~ENABLE_UNSUP_TX_ERRORS; |
| 282 | val |= ENABLE_WRAP_TO_INCR_BURSTS; |
| 283 | mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); |
| 284 | |
| 285 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 286 | * Restore Boot and Power Management Processor (BPMP) reset |
| 287 | * address and reset it. |
| 288 | */ |
| 289 | tegra_fc_reset_bpmp(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | /* |
| 293 | * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's |
| 294 | * used for power management and boot purposes. Inform the BPMP that |
| 295 | * we have completed the cluster power up. |
| 296 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 297 | tegra_fc_lock_active_cluster(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 298 | |
| 299 | return PSCI_E_SUCCESS; |
| 300 | } |
| 301 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 302 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 303 | { |
| 304 | int cpu = mpidr & MPIDR_CPU_MASK; |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 305 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 306 | |
| 307 | /* Deassert CPU reset signals */ |
| 308 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 309 | |
| 310 | /* Turn on CPU using flow controller or PMC */ |
| 311 | if (cpu_powergate_mask[cpu] == 0) { |
| 312 | tegra_pmc_cpu_on(cpu); |
| 313 | cpu_powergate_mask[cpu] = 1; |
| 314 | } else { |
| 315 | tegra_fc_cpu_on(cpu); |
| 316 | } |
| 317 | |
| 318 | return PSCI_E_SUCCESS; |
| 319 | } |
| 320 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 321 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 322 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 323 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 324 | return PSCI_E_SUCCESS; |
| 325 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 326 | |
| 327 | int tegra_soc_prepare_system_reset(void) |
| 328 | { |
| 329 | /* |
| 330 | * Set System Clock (SCLK) to POR default so that the clock source |
| 331 | * for the PMC APB clock would not be changed due to system reset. |
| 332 | */ |
| 333 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 334 | SCLK_BURST_POLICY_DEFAULT); |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 335 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 336 | |
| 337 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 338 | mdelay(1); |
| 339 | |
| 340 | return PSCI_E_SUCCESS; |
| 341 | } |