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Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
Toshiyuki Ogasahara77626582020-11-30 20:39:21 +09002 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef RCAR_DEF_H
8#define RCAR_DEF_H
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
11#include <lib/utils_def.h>
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020012
13#define RCAR_PRIMARY_CPU 0x0
14#define RCAR_TRUSTED_SRAM_BASE 0x44000000
15#define RCAR_TRUSTED_SRAM_SIZE 0x0003E000
16#define RCAR_SHARED_MEM_BASE (RCAR_TRUSTED_SRAM_BASE + \
17 RCAR_TRUSTED_SRAM_SIZE)
18#define RCAR_SHARED_MEM_SIZE U(0x00001000)
19#define FLASH0_BASE U(0x08000000)
20#define FLASH0_SIZE U(0x04000000)
21#define FLASH_MEMORY_SIZE U(0x04000000) /* hyper flash */
22#define FLASH_TRANS_SIZE_UNIT U(0x00000100)
23#define DEVICE_RCAR_BASE U(0xE6000000)
24#define DEVICE_RCAR_SIZE U(0x00300000)
25#define DEVICE_RCAR_BASE2 U(0xE6360000)
26#define DEVICE_RCAR_SIZE2 U(0x19CA0000)
Marek Vasut2e032c02018-12-26 15:57:08 +010027#define DEVICE_SRAM_BASE U(0xE6300000)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020028#define DEVICE_SRAM_SIZE U(0x00002000)
29#define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
30#define DEVICE_SRAM_STACK_SIZE U(0x00001000)
31#define DRAM_LIMIT ULL(0x0000010000000000)
32#define DRAM1_BASE U(0x40000000)
33#define DRAM1_SIZE U(0x80000000)
34#define DRAM1_NS_BASE (DRAM1_BASE + U(0x10000000))
35#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE)
Biju Das00e6aea2020-12-13 20:49:27 +000036#define DRAM_40BIT_BASE ULL(0x0400000000)
37#define DRAM_40BIT_SIZE ULL(0x0400000000)
38#define DRAM_PROTECTED_BASE ULL(0x43F00000)
39#define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000)
40#define DRAM_PROTECTED_SIZE ULL(0x03F00000)
41#define RCAR_BL31_CRASH_BASE U(0x4403F000)
42#define RCAR_BL31_CRASH_SIZE U(0x00001000)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020043/* Entrypoint mailboxes */
44#define MBOX_BASE RCAR_SHARED_MEM_BASE
45#define MBOX_SIZE 0x200
46/* Base address where parameters to BL31 are stored */
47#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
48#define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \
49 RCAR_SHARED_MEM_SIZE - 0x100)
Biju Das00e6aea2020-12-13 20:49:27 +000050/*
51 * The number of regions like RO(code), coherent and data required by
52 * different BL stages which need to be mapped in the MMU
53 */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020054#if USE_COHERENT_MEM
55#define RCAR_BL_REGIONS (3)
56#else
57#define RCAR_BL_REGIONS (2)
58#endif
Biju Das00e6aea2020-12-13 20:49:27 +000059/*
60 * The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[]
61 * defined for each BL stage in rcar_common.c.
62 */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020063#if IMAGE_BL2
64#define RCAR_MMAP_ENTRIES (9)
65#endif
66#if IMAGE_BL31
67#define RCAR_MMAP_ENTRIES (9)
68#endif
69#if IMAGE_BL2
70#define REG1_BASE U(0xE6400000)
71#define REG1_SIZE U(0x04C00000)
72#define ROM0_BASE U(0xEB100000)
73#define ROM0_SIZE U(0x00028000)
74#define REG2_BASE U(0xEC000000)
75#define REG2_SIZE U(0x14000000)
76#endif
77/* BL33 */
78#define NS_IMAGE_OFFSET (DRAM1_BASE + U(0x09000000))
79/* BL31 */
Biju Das00e6aea2020-12-13 20:49:27 +000080#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
81#define RCAR_DEVICE_SIZE (0x1A000000)
82#define RCAR_LOG_RES_SIZE (64)
83#define RCAR_LOG_HEADER_SIZE (16)
84#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020085 RCAR_LOG_RES_SIZE)
Biju Das00e6aea2020-12-13 20:49:27 +000086#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020087 RCAR_LOG_OTHER_SIZE)
Biju Das00e6aea2020-12-13 20:49:27 +000088#define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE
89#define AARCH64_SPACE_BASE ULL(0x00000000000)
90#define AARCH64_SPACE_SIZE ULL(0x10000000000)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020091/* CCI related constants */
92#define CCI500_BASE U(0xF1200000)
93#define CCI500_CLUSTER0_SL_IFACE_IX (2)
94#define CCI500_CLUSTER1_SL_IFACE_IX (3)
95#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 (1)
96#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 (2)
Biju Das00e6aea2020-12-13 20:49:27 +000097#define RCAR_CCI_BASE CCI500_BASE
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020098/* GIC */
99#define RCAR_GICD_BASE U(0xF1010000)
100#define RCAR_GICR_BASE U(0xF1010000)
101#define RCAR_GICC_BASE U(0xF1020000)
102#define RCAR_GICH_BASE U(0xF1040000)
103#define RCAR_GICV_BASE U(0xF1060000)
104#define ARM_IRQ_SEC_PHY_TIMER U(29)
105#define ARM_IRQ_SEC_SGI_0 U(8)
106#define ARM_IRQ_SEC_SGI_1 U(9)
107#define ARM_IRQ_SEC_SGI_2 U(10)
108#define ARM_IRQ_SEC_SGI_3 U(11)
109#define ARM_IRQ_SEC_SGI_4 U(12)
110#define ARM_IRQ_SEC_SGI_5 U(13)
111#define ARM_IRQ_SEC_SGI_6 U(14)
112#define ARM_IRQ_SEC_SGI_7 U(15)
Biju Das00e6aea2020-12-13 20:49:27 +0000113#define ARM_IRQ_SEC_RPC U(70)
114#define ARM_IRQ_SEC_TIMER U(166)
115#define ARM_IRQ_SEC_TIMER_UP U(171)
116#define ARM_IRQ_SEC_WDT U(173)
117#define ARM_IRQ_SEC_CRYPT U(102)
118#define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
119#define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200120/* Timer control */
Biju Das00e6aea2020-12-13 20:49:27 +0000121#define RCAR_CNTC_BASE U(0xE6080000)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200122/* Reset */
Biju Das00e6aea2020-12-13 20:49:27 +0000123#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
124#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
125#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
126#define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
127#define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
128#define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
129#define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
130#define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
131#define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
132#define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
133#define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
134#define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
135#define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
136#define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200137/* SYSC */
Biju Das00e6aea2020-12-13 20:49:27 +0000138#define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
139#define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
140#define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
141#define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
142#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
143#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
144#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
145#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutoff A53-SCU */
146#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutoff A57-SCU */
147#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
148#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
149#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
150#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200151/* Product register */
Biju Das00e6aea2020-12-13 20:49:27 +0000152#define RCAR_PRR U(0xFFF00044)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200153#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
Toshiyuki Ogasaharac3c52272021-07-12 19:18:57 +0900154#define RCAR_D3_CUT_VER10 U(0x00000000) /* D3 Ver.1.0 */
155#define RCAR_D3_CUT_VER11 U(0x00000010) /* D3 Ver.1.1 */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200156#define RCAR_MAJOR_MASK U(0x000000F0)
157#define RCAR_MINOR_MASK U(0x0000000F)
Marek Vasut9cadc782019-08-06 19:13:22 +0200158#define PRR_PRODUCT_SHIFT U(8)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200159#define RCAR_MAJOR_SHIFT U(4)
160#define RCAR_MINOR_SHIFT U(0)
161#define RCAR_MAJOR_OFFSET U(1)
Marek Vasut3af20052019-02-25 14:57:08 +0100162#define RCAR_M3_MINOR_OFFSET U(2)
Marek Vasut9cadc782019-08-06 19:13:22 +0200163#define PRR_PRODUCT_H3_CUT10 (PRR_PRODUCT_H3 | U(0x00)) /* 1.0 */
164#define PRR_PRODUCT_H3_CUT11 (PRR_PRODUCT_H3 | U(0x01)) /* 1.1 */
165#define PRR_PRODUCT_H3_CUT20 (PRR_PRODUCT_H3 | U(0x10)) /* 2.0 */
166#define PRR_PRODUCT_M3_CUT10 (PRR_PRODUCT_M3 | U(0x00)) /* 1.0 */
167#define PRR_PRODUCT_M3_CUT11 (PRR_PRODUCT_M3 | U(0x10))
Marek Vasutd97f6ee2019-08-06 18:58:38 +0200168#define PRR 0xFFF00044U
169#define PRR_PRODUCT_MASK 0x00007F00U
170#define PRR_CUT_MASK 0x000000FFU
171#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */
172#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3-W */
173#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */
174#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3-N */
175#define PRR_PRODUCT_V3H 0x00005600U /* R-Car V3H */
176#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */
177#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */
178#define PRR_PRODUCT_10 0x00U /* Ver.1.0 */
179#define PRR_PRODUCT_11 0x01U /* Ver.1.1 */
180#define PRR_PRODUCT_20 0x10U /* Ver.2.0 */
181#define PRR_PRODUCT_21 0x11U /* Ver.2.1 */
182#define PRR_PRODUCT_30 0x20U /* Ver.3.0 */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200183#define RCAR_CPU_MASK_CA57 U(0x80000000)
184#define RCAR_CPU_MASK_CA53 U(0x04000000)
185#define RCAR_CPU_HAVE_CA57 U(0x00000000)
186#define RCAR_CPU_HAVE_CA53 U(0x00000000)
187#define RCAR_SSCG_MASK U(0x1000) /* MD12 */
188#define RCAR_SSCG_ENABLE U(0x1000)
189/* MD pin information */
190#define MODEMR_BOOT_CPU_MASK U(0x000000C0)
191#define MODEMR_BOOT_CPU_CR7 U(0x000000C0)
192#define MODEMR_BOOT_CPU_CA57 U(0x00000000)
193#define MODEMR_BOOT_CPU_CA53 U(0x00000040)
194#define MODEMR_BOOT_DEV_MASK U(0x0000001E)
195#define MODEMR_BOOT_DEV_HYPERFLASH160 U(0x00000004)
196#define MODEMR_BOOT_DEV_HYPERFLASH80 U(0x00000006)
197#define MODEMR_BOOT_DEV_QSPI_FLASH40 U(0x00000008)
198#define MODEMR_BOOT_DEV_QSPI_FLASH80 U(0x0000000C)
199#define MODEMR_BOOT_DEV_EMMC_25X1 U(0x0000000A)
200#define MODEMR_BOOT_DEV_EMMC_50X8 U(0x0000001A)
201#define MODEMR_BOOT_PLL_MASK U(0x00006000)
202#define MODEMR_BOOT_PLL_SHIFT U(13)
203/* Memory mapped Generic timer interfaces */
204#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE
205/* MODEMR PLL masks and bitfield values */
Biju Das00e6aea2020-12-13 20:49:27 +0000206#define CHECK_MD13_MD14 U(0x6000)
207#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
208#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
209#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
210#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200211/* Frequency of EXTAL(Hz) */
Biju Das00e6aea2020-12-13 20:49:27 +0000212#define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
213#define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
214#define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
215#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
216#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200217#define EXTAL_EBISU U(24000000) /* Ebisu */
Marek Vasut4ae342c2019-01-05 13:56:03 +0100218#define EXTAL_DRAAK U(24000000) /* Draak */
Biju Das00e6aea2020-12-13 20:49:27 +0000219/* CPG write protect registers */
220#define CPGWPR_PASSWORD (0x5A5AFFFFU)
221#define CPGWPCR_PASSWORD (0xA5A50000U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200222/* CA5x Debug Resource control registers */
Biju Das00e6aea2020-12-13 20:49:27 +0000223#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
224#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
225#define DBGCPUPREN ((uint32_t)1U << 19U)
226#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
227#define CPG_PLL2CR (CPG_BASE + 0x002CU)
228#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
Marek Vasutdcc9ef82019-08-07 18:19:26 +0200229#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200230/* RST Registers */
Biju Das00e6aea2020-12-13 20:49:27 +0000231#define RST_BASE (0xE6160000U)
232#define RST_WDTRSTCR (RST_BASE + 0x0054U)
Marek Vasutdcc9ef82019-08-07 18:19:26 +0200233#define RST_MODEMR (RST_BASE + 0x0060U)
Biju Das00e6aea2020-12-13 20:49:27 +0000234#define WDTRSTCR_PASSWORD (0xA55A0000U)
235#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200236/* MFIS Registers */
Biju Das00e6aea2020-12-13 20:49:27 +0000237#define MFISWPCNTR_PASSWORD (0xACCE0000U)
238#define MFISWPCNTR (0xE6260900U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200239/* IPMMU registers */
240#define IPMMU_MM_BASE (0xE67B0000U)
241#define IPMMUMM_IMSCTLR (IPMMU_MM_BASE + 0x0500U)
242#define IPMMUMM_IMAUXCTLR (IPMMU_MM_BASE + 0x0504U)
243#define IPMMUMM_IMSCTLR_ENABLE (0xC0000000U)
244#define IPMMUMM_IMAUXCTLR_NMERGE40_BIT (0x01000000U)
245#define IMSCTLR_DISCACHE (0xE0000000U)
Marek Vasute6208012018-12-31 16:48:04 +0100246#define IPMMU_VP0_BASE (0xFE990000U)
247#define IPMMUVP0_IMSCTLR (IPMMU_VP0_BASE + 0x0500U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200248#define IPMMU_VI0_BASE (0xFEBD0000U)
249#define IPMMUVI0_IMSCTLR (IPMMU_VI0_BASE + 0x0500U)
250#define IPMMU_VI1_BASE (0xFEBE0000U)
251#define IPMMUVI1_IMSCTLR (IPMMU_VI1_BASE + 0x0500U)
252#define IPMMU_PV0_BASE (0xFD800000U)
253#define IPMMUPV0_IMSCTLR (IPMMU_PV0_BASE + 0x0500U)
254#define IPMMU_PV1_BASE (0xFD950000U)
255#define IPMMUPV1_IMSCTLR (IPMMU_PV1_BASE + 0x0500U)
256#define IPMMU_PV2_BASE (0xFD960000U)
257#define IPMMUPV2_IMSCTLR (IPMMU_PV2_BASE + 0x0500U)
258#define IPMMU_PV3_BASE (0xFD970000U)
259#define IPMMUPV3_IMSCTLR (IPMMU_PV3_BASE + 0x0500U)
260#define IPMMU_HC_BASE (0xE6570000U)
261#define IPMMUHC_IMSCTLR (IPMMU_HC_BASE + 0x0500U)
262#define IPMMU_RT_BASE (0xFFC80000U)
263#define IPMMURT_IMSCTLR (IPMMU_RT_BASE + 0x0500U)
264#define IPMMU_MP_BASE (0xEC670000U)
265#define IPMMUMP_IMSCTLR (IPMMU_MP_BASE + 0x0500U)
266#define IPMMU_DS0_BASE (0xE6740000U)
267#define IPMMUDS0_IMSCTLR (IPMMU_DS0_BASE + 0x0500U)
268#define IPMMU_DS1_BASE (0xE7740000U)
269#define IPMMUDS1_IMSCTLR (IPMMU_DS1_BASE + 0x0500U)
270/* ARMREG registers */
Biju Das00e6aea2020-12-13 20:49:27 +0000271#define P_ARMREG_SEC_CTRL (0xE62711F0U)
272#define P_ARMREG_SEC_CTRL_PROT (0x00000001U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200273/* MIDR */
274#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
275#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
276/* for SuspendToRAM */
Marek Vasuta2e5d192019-08-07 18:05:05 +0200277#define GPIO_BASE (0xE6050000U)
278#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
279#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200280#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
Marek Vasuta2e5d192019-08-07 18:05:05 +0200281#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
282#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
283#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
284#define RCAR_COLD_BOOT (0x00U)
285#define RCAR_WARM_BOOT (0x01U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200286#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
Biju Das00e6aea2020-12-13 20:49:27 +0000287#define KEEP10_MAGIC (0x55U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200288#endif
289/* lossy registers */
Biju Das00e6aea2020-12-13 20:49:27 +0000290#define LOSSY_PARAMS_BASE (0x47FD7000U)
291#define AXI_DCMPAREACRA0 (0xE6784100U)
292#define AXI_DCMPAREACRB0 (0xE6784104U)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200293#define LOSSY_ENABLE (0x80000000U)
294#define LOSSY_DISABLE (0x00000000U)
295#define LOSSY_FMT_YUVPLANAR (0x00000000U)
296#define LOSSY_FMT_YUV422INTLV (0x20000000U)
297#define LOSSY_FMT_ARGB8888 (0x40000000U)
Biju Das00e6aea2020-12-13 20:49:27 +0000298#define LOSSY_ST_ADDR0 (0x54000000U)
299#define LOSSY_END_ADDR0 (0x57000000U)
300#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR
301#define LOSSY_ENA_DIS0 LOSSY_ENABLE
302#define LOSSY_ST_ADDR1 0x0U
303#define LOSSY_END_ADDR1 0x0U
304#define LOSSY_FMT1 LOSSY_FMT_ARGB8888
305#define LOSSY_ENA_DIS1 LOSSY_DISABLE
306#define LOSSY_ST_ADDR2 0x0U
307#define LOSSY_END_ADDR2 0x0U
308#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
309#define LOSSY_ENA_DIS2 LOSSY_DISABLE
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200310
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000311#endif /* RCAR_DEF_H */