blob: 44339a12646f1a42c97d5f3497ab69f44d6f064b [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31/dts-v1/;
32
33/memreserve/ 0x80000000 0x00010000;
34
35/ {
36};
37
38/ {
39 model = "FVP Base";
40 compatible = "arm,vfp-base", "arm,vexpress";
41 interrupt-parent = <&gic>;
42 #address-cells = <2>;
43 #size-cells = <2>;
44
45 chosen { };
46
47 aliases {
48 serial0 = &v2m_serial0;
49 serial1 = &v2m_serial1;
50 serial2 = &v2m_serial2;
51 serial3 = &v2m_serial3;
52 };
53
54 psci {
55 compatible = "arm,psci";
56 method = "smc";
57 cpu_suspend = <0xc4000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0xc4000003>;
60 };
61
62 cpus {
63 #address-cells = <2>;
64 #size-cells = <0>;
65
66 cpu@0 {
67 device_type = "cpu";
68 compatible = "arm,armv8";
69 reg = <0x0 0x0>;
70 enable-method = "psci";
71 };
72 cpu@1 {
73 device_type = "cpu";
74 compatible = "arm,armv8";
75 reg = <0x0 0x1>;
76 enable-method = "psci";
77 };
78 cpu@2 {
79 device_type = "cpu";
80 compatible = "arm,armv8";
81 reg = <0x0 0x2>;
82 enable-method = "psci";
83 };
84 cpu@3 {
85 device_type = "cpu";
86 compatible = "arm,armv8";
87 reg = <0x0 0x3>;
88 enable-method = "psci";
89 };
90 cpu@100 {
91 device_type = "cpu";
92 compatible = "arm,armv8";
93 reg = <0x0 0x100>;
94 enable-method = "psci";
95 };
96 cpu@101 {
97 device_type = "cpu";
98 compatible = "arm,armv8";
99 reg = <0x0 0x101>;
100 enable-method = "psci";
101 };
102 cpu@102 {
103 device_type = "cpu";
104 compatible = "arm,armv8";
105 reg = <0x0 0x102>;
106 enable-method = "psci";
107 };
108 cpu@103 {
109 device_type = "cpu";
110 compatible = "arm,armv8";
111 reg = <0x0 0x103>;
112 enable-method = "psci";
113 };
114 };
115
116 memory@80000000 {
117 device_type = "memory";
Juan Castillo7055ca42014-05-16 15:33:15 +0100118 reg = <0x00000000 0x80000000 0 0x7F000000>,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119 <0x00000008 0x80000000 0 0x80000000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100120 };
121
Harry Liebel34988592013-11-11 13:24:47 +0000122 gic: interrupt-controller@2f000000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123 compatible = "arm,gic-v3";
124 #interrupt-cells = <3>;
Harry Liebel34988592013-11-11 13:24:47 +0000125 #address-cells = <2>;
126 #size-cells = <2>;
127 ranges;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128 interrupt-controller;
129 reg = <0x0 0x2f000000 0 0x10000>, // GICD
130 <0x0 0x2f100000 0 0x200000>, // GICR
131 <0x0 0x2c000000 0 0x2000>, // GICC
132 <0x0 0x2c010000 0 0x2000>, // GICH
Harry Liebel34988592013-11-11 13:24:47 +0000133 <0x0 0x2c02f000 0 0x2000>; // GICV
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134 interrupts = <1 9 4>;
Harry Liebel34988592013-11-11 13:24:47 +0000135
136 its: its@2f020000 {
137 compatible = "arm,gic-v3-its";
138 msi-controller;
139 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
140 };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141 };
142
143 timer {
144 compatible = "arm,armv8-timer";
145 interrupts = <1 13 0xff01>,
146 <1 14 0xff01>,
147 <1 11 0xff01>,
148 <1 10 0xff01>;
149 clock-frequency = <100000000>;
150 };
151
152 timer@2a810000 {
153 compatible = "arm,armv7-timer-mem";
154 reg = <0x0 0x2a810000 0x0 0x10000>;
155 clock-frequency = <100000000>;
156 #address-cells = <2>;
157 #size-cells = <2>;
158 ranges;
Harry Liebelcef93392014-04-01 19:27:38 +0100159 frame@2a830000 {
160 frame-number = <1>;
161 interrupts = <0 26 4>;
162 reg = <0x0 0x2a830000 0x0 0x10000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163 };
164 };
165
166 pmu {
167 compatible = "arm,armv8-pmuv3";
168 interrupts = <0 60 4>,
169 <0 61 4>,
170 <0 62 4>,
171 <0 63 4>;
172 };
173
174 smb {
175 compatible = "simple-bus";
176
177 #address-cells = <2>;
178 #size-cells = <1>;
179 ranges = <0 0 0 0x08000000 0x04000000>,
180 <1 0 0 0x14000000 0x04000000>,
181 <2 0 0 0x18000000 0x04000000>,
182 <3 0 0 0x1c000000 0x04000000>,
183 <4 0 0 0x0c000000 0x04000000>,
184 <5 0 0 0x10000000 0x04000000>;
185
186 #interrupt-cells = <1>;
187 interrupt-map-mask = <0 0 63>;
Harry Liebel34988592013-11-11 13:24:47 +0000188 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
189 <0 0 1 &gic 0 0 0 1 4>,
190 <0 0 2 &gic 0 0 0 2 4>,
191 <0 0 3 &gic 0 0 0 3 4>,
192 <0 0 4 &gic 0 0 0 4 4>,
193 <0 0 5 &gic 0 0 0 5 4>,
194 <0 0 6 &gic 0 0 0 6 4>,
195 <0 0 7 &gic 0 0 0 7 4>,
196 <0 0 8 &gic 0 0 0 8 4>,
197 <0 0 9 &gic 0 0 0 9 4>,
198 <0 0 10 &gic 0 0 0 10 4>,
199 <0 0 11 &gic 0 0 0 11 4>,
200 <0 0 12 &gic 0 0 0 12 4>,
201 <0 0 13 &gic 0 0 0 13 4>,
202 <0 0 14 &gic 0 0 0 14 4>,
203 <0 0 15 &gic 0 0 0 15 4>,
204 <0 0 16 &gic 0 0 0 16 4>,
205 <0 0 17 &gic 0 0 0 17 4>,
206 <0 0 18 &gic 0 0 0 18 4>,
207 <0 0 19 &gic 0 0 0 19 4>,
208 <0 0 20 &gic 0 0 0 20 4>,
209 <0 0 21 &gic 0 0 0 21 4>,
210 <0 0 22 &gic 0 0 0 22 4>,
211 <0 0 23 &gic 0 0 0 23 4>,
212 <0 0 24 &gic 0 0 0 24 4>,
213 <0 0 25 &gic 0 0 0 25 4>,
214 <0 0 26 &gic 0 0 0 26 4>,
215 <0 0 27 &gic 0 0 0 27 4>,
216 <0 0 28 &gic 0 0 0 28 4>,
217 <0 0 29 &gic 0 0 0 29 4>,
218 <0 0 30 &gic 0 0 0 30 4>,
219 <0 0 31 &gic 0 0 0 31 4>,
220 <0 0 32 &gic 0 0 0 32 4>,
221 <0 0 33 &gic 0 0 0 33 4>,
222 <0 0 34 &gic 0 0 0 34 4>,
223 <0 0 35 &gic 0 0 0 35 4>,
224 <0 0 36 &gic 0 0 0 36 4>,
225 <0 0 37 &gic 0 0 0 37 4>,
226 <0 0 38 &gic 0 0 0 38 4>,
227 <0 0 39 &gic 0 0 0 39 4>,
228 <0 0 40 &gic 0 0 0 40 4>,
229 <0 0 41 &gic 0 0 0 41 4>,
230 <0 0 42 &gic 0 0 0 42 4>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100231
Juan Castillo4dc4a472014-08-12 11:17:06 +0100232 /include/ "rtsm_ve-motherboard-no_psci.dtsi"
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233 };
234
235 panels {
236 panel@0 {
237 compatible = "panel";
238 mode = "XVGA";
239 refresh = <60>;
240 xres = <1024>;
241 yres = <768>;
242 pixclock = <15748>;
243 left_margin = <152>;
244 right_margin = <48>;
245 upper_margin = <23>;
246 lower_margin = <3>;
247 hsync_len = <104>;
248 vsync_len = <4>;
249 sync = <0>;
250 vmode = "FB_VMODE_NONINTERLACED";
251 tim2 = "TIM2_BCD", "TIM2_IPC";
252 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
253 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
254 bpp = <16>;
255 };
256 };
257};