Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <errno.h> |
| 8 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 9 | #include <arch.h> |
| 10 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <common/debug.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 12 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <lib/mmio.h> |
| 14 | |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 15 | #include <mce_private.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 16 | #include <t18x_ari.h> |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 17 | #include <tegra_private.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 18 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 19 | int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 20 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 21 | int32_t ret = 0; |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 22 | uint64_t val = 0ULL; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 23 | |
| 24 | (void)ari_base; |
| 25 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 26 | /* check for allowed power state */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 27 | if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && |
| 28 | (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 29 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 30 | ret = EINVAL; |
| 31 | } else { |
| 32 | /* time (TSC ticks) until the core is expected to get a wake event */ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 33 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 34 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 35 | /* set the core cstate */ |
Steven Kao | d417cea | 2017-06-14 14:02:23 +0800 | [diff] [blame] | 36 | val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK; |
| 37 | write_actlr_el1(val | (uint64_t)state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 38 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 39 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 40 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 41 | } |
| 42 | |
| 43 | /* |
| 44 | * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and |
| 45 | * SYSTEM_CSTATE values. |
| 46 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 47 | int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 48 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 49 | uint8_t update_wake_mask) |
| 50 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 51 | uint64_t val = 0ULL; |
| 52 | |
| 53 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 54 | |
| 55 | /* update CLUSTER_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 56 | if (cluster != 0U) { |
| 57 | val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 58 | CLUSTER_CSTATE_UPDATE_BIT; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 59 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 60 | |
| 61 | /* update CCPLEX_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 62 | if (ccplex != 0U) { |
| 63 | val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 64 | CCPLEX_CSTATE_UPDATE_BIT; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 65 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 66 | |
| 67 | /* update SYSTEM_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 68 | if (system != 0U) { |
| 69 | val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | |
| 70 | (((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 71 | SYSTEM_CSTATE_UPDATE_BIT); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 72 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 73 | |
| 74 | /* update wake mask value? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 75 | if (update_wake_mask != 0U) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 76 | val |= CSTATE_WAKE_MASK_UPDATE_BIT; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 77 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 78 | |
| 79 | /* set the wake mask */ |
| 80 | val &= CSTATE_WAKE_MASK_CLEAR; |
| 81 | val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT); |
| 82 | |
| 83 | /* set the updated cstate info */ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 84 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 89 | int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 90 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 91 | int32_t ret = 0; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 92 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 93 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 94 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 95 | /* sanity check crossover type */ |
| 96 | if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) { |
| 97 | ret = EINVAL; |
| 98 | } else { |
| 99 | /* |
| 100 | * The crossover threshold limit types start from |
| 101 | * TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. |
| 102 | * The command indices for updating the threshold be generated |
| 103 | * by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6 |
| 104 | * command index. |
| 105 | */ |
| 106 | nvg_set_request_data((TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + |
| 107 | (uint64_t)type), (uint64_t)time); |
| 108 | } |
| 109 | |
| 110 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) |
| 114 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 115 | uint64_t ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 116 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 117 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 118 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 119 | /* sanity check state */ |
| 120 | if (state == 0U) { |
| 121 | ret = EINVAL; |
| 122 | } else { |
| 123 | /* |
| 124 | * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES |
| 125 | * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for |
| 126 | * reading the threshold can be generated by adding the type to |
| 127 | * the NVG_CLEAR_CSTATE_STATS command index. |
| 128 | */ |
| 129 | nvg_set_request((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + |
| 130 | (uint64_t)state)); |
| 131 | ret = nvg_get_result(); |
| 132 | } |
| 133 | |
| 134 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 135 | } |
| 136 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 137 | int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 138 | { |
| 139 | uint64_t val; |
| 140 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 141 | (void)ari_base; |
| 142 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 143 | /* |
| 144 | * The only difference between a CSTATE_STATS_WRITE and |
| 145 | * CSTATE_STATS_READ is the usage of the 63:32 in the request. |
| 146 | * 63:32 are set to '0' for a read, while a write contains the |
| 147 | * actual stats value to be written. |
| 148 | */ |
| 149 | val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state; |
| 150 | |
| 151 | /* |
| 152 | * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES |
| 153 | * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for |
| 154 | * reading the threshold can be generated by adding the type to |
| 155 | * the NVG_CLEAR_CSTATE_STATS command index. |
| 156 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 157 | nvg_set_request_data((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + |
| 158 | (uint64_t)state), val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 159 | |
| 160 | return 0; |
| 161 | } |
| 162 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 163 | int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 164 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 165 | (void)ari_base; |
| 166 | (void)state; |
| 167 | (void)wake_time; |
| 168 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 169 | /* This does not apply to the Denver cluster */ |
| 170 | return 0; |
| 171 | } |
| 172 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 173 | int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 174 | { |
| 175 | uint64_t val; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 176 | int32_t ret; |
| 177 | |
| 178 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 179 | |
| 180 | /* check for allowed power state */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 181 | if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && |
| 182 | (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 183 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 184 | ret = EINVAL; |
| 185 | } else { |
| 186 | /* |
| 187 | * Request format - |
| 188 | * 63:32 = wake time |
| 189 | * 31:0 = C-state for this core |
| 190 | */ |
| 191 | val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) | |
| 192 | ((uint64_t)state & MCE_SC7_ALLOWED_MASK); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 193 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 194 | /* issue command to check if SC7 is allowed */ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 195 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 196 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 197 | /* 1 = SC7 allowed, 0 = SC7 not allowed */ |
| 198 | ret = (nvg_get_result() != 0ULL) ? 1 : 0; |
| 199 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 200 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 201 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 202 | } |
| 203 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 204 | int32_t nvg_online_core(uint32_t ari_base, uint32_t core) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 205 | { |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 206 | uint64_t cpu = read_mpidr() & MPIDR_CPU_MASK; |
| 207 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 208 | int32_t ret = 0; |
| 209 | |
| 210 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 211 | |
| 212 | /* sanity check code id */ |
Anthony Zhou | 3b80450 | 2017-06-26 20:33:34 +0800 | [diff] [blame] | 213 | if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 214 | ERROR("%s: unsupported core id (%d)\n", __func__, core); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 215 | ret = EINVAL; |
| 216 | } else { |
| 217 | /* |
| 218 | * The Denver cluster has 2 CPUs only - 0, 1. |
| 219 | */ |
| 220 | if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) { |
| 221 | ERROR("%s: unknown core id (%d)\n", __func__, core); |
| 222 | ret = EINVAL; |
| 223 | } else { |
| 224 | /* get a core online */ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 225 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE, |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 226 | ((uint64_t)core & MCE_CORE_ID_MASK)); |
| 227 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 228 | } |
| 229 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 230 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 231 | } |
| 232 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 233 | int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 234 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 235 | uint32_t val; |
| 236 | |
| 237 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 238 | |
| 239 | /* |
| 240 | * If the enable bit is cleared, Auto-CC3 will be disabled by setting |
| 241 | * the SW visible voltage/frequency request registers for all non |
| 242 | * floorswept cores valid independent of StandbyWFI and disabling |
| 243 | * the IDLE voltage/frequency request register. If set, Auto-CC3 |
| 244 | * will be enabled by setting the ARM SW visible voltage/frequency |
| 245 | * request registers for all non floorswept cores to be enabled by |
| 246 | * StandbyWFI or the equivalent signal, and always keeping the IDLE |
| 247 | * voltage/frequency request register enabled. |
| 248 | */ |
Elyes Haouas | 183638f | 2023-02-13 10:05:41 +0100 | [diff] [blame] | 249 | val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) | |
| 250 | ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 251 | ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 252 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 253 | nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 254 | |
| 255 | return 0; |
| 256 | } |