Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame^] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <debug.h> |
| 10 | #include <denver.h> |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame^] | 11 | #include <errno.h> |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 12 | #include <mce_private.h> |
Isla Mitchell | e363146 | 2017-07-14 10:46:32 +0100 | [diff] [blame] | 13 | #include <mmio.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 14 | #include <t18x_ari.h> |
| 15 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 16 | int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 17 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 18 | int32_t ret = 0; |
| 19 | |
| 20 | (void)ari_base; |
| 21 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 22 | /* check for allowed power state */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 23 | if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && |
| 24 | (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 25 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 26 | ret = EINVAL; |
| 27 | } else { |
| 28 | /* time (TSC ticks) until the core is expected to get a wake event */ |
| 29 | nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 30 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 31 | /* set the core cstate */ |
| 32 | write_actlr_el1(state); |
| 33 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 34 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 35 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 36 | } |
| 37 | |
| 38 | /* |
| 39 | * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and |
| 40 | * SYSTEM_CSTATE values. |
| 41 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 42 | int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 43 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 44 | uint8_t update_wake_mask) |
| 45 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 46 | uint64_t val = 0ULL; |
| 47 | |
| 48 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 49 | |
| 50 | /* update CLUSTER_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 51 | if (cluster != 0U) { |
| 52 | val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 53 | CLUSTER_CSTATE_UPDATE_BIT; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 54 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 55 | |
| 56 | /* update CCPLEX_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 57 | if (ccplex != 0U) { |
| 58 | val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 59 | CCPLEX_CSTATE_UPDATE_BIT; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 60 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 61 | |
| 62 | /* update SYSTEM_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 63 | if (system != 0U) { |
| 64 | val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | |
| 65 | (((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 66 | SYSTEM_CSTATE_UPDATE_BIT); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 67 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 68 | |
| 69 | /* update wake mask value? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 70 | if (update_wake_mask != 0U) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 71 | val |= CSTATE_WAKE_MASK_UPDATE_BIT; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 72 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 73 | |
| 74 | /* set the wake mask */ |
| 75 | val &= CSTATE_WAKE_MASK_CLEAR; |
| 76 | val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT); |
| 77 | |
| 78 | /* set the updated cstate info */ |
| 79 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val); |
| 80 | |
| 81 | return 0; |
| 82 | } |
| 83 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 84 | int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 85 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 86 | int32_t ret = 0; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 87 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 88 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 89 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 90 | /* sanity check crossover type */ |
| 91 | if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) { |
| 92 | ret = EINVAL; |
| 93 | } else { |
| 94 | /* |
| 95 | * The crossover threshold limit types start from |
| 96 | * TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. |
| 97 | * The command indices for updating the threshold be generated |
| 98 | * by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6 |
| 99 | * command index. |
| 100 | */ |
| 101 | nvg_set_request_data((TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + |
| 102 | (uint64_t)type), (uint64_t)time); |
| 103 | } |
| 104 | |
| 105 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) |
| 109 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 110 | uint64_t ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 111 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 112 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 113 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 114 | /* sanity check state */ |
| 115 | if (state == 0U) { |
| 116 | ret = EINVAL; |
| 117 | } else { |
| 118 | /* |
| 119 | * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES |
| 120 | * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for |
| 121 | * reading the threshold can be generated by adding the type to |
| 122 | * the NVG_CLEAR_CSTATE_STATS command index. |
| 123 | */ |
| 124 | nvg_set_request((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + |
| 125 | (uint64_t)state)); |
| 126 | ret = nvg_get_result(); |
| 127 | } |
| 128 | |
| 129 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 130 | } |
| 131 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 132 | int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 133 | { |
| 134 | uint64_t val; |
| 135 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 136 | (void)ari_base; |
| 137 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 138 | /* |
| 139 | * The only difference between a CSTATE_STATS_WRITE and |
| 140 | * CSTATE_STATS_READ is the usage of the 63:32 in the request. |
| 141 | * 63:32 are set to '0' for a read, while a write contains the |
| 142 | * actual stats value to be written. |
| 143 | */ |
| 144 | val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state; |
| 145 | |
| 146 | /* |
| 147 | * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES |
| 148 | * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for |
| 149 | * reading the threshold can be generated by adding the type to |
| 150 | * the NVG_CLEAR_CSTATE_STATS command index. |
| 151 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 152 | nvg_set_request_data((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + |
| 153 | (uint64_t)state), val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 158 | int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 159 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 160 | (void)ari_base; |
| 161 | (void)state; |
| 162 | (void)wake_time; |
| 163 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 164 | /* This does not apply to the Denver cluster */ |
| 165 | return 0; |
| 166 | } |
| 167 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 168 | int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 169 | { |
| 170 | uint64_t val; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 171 | int32_t ret; |
| 172 | |
| 173 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 174 | |
| 175 | /* check for allowed power state */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 176 | if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && |
| 177 | (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 178 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 179 | ret = EINVAL; |
| 180 | } else { |
| 181 | /* |
| 182 | * Request format - |
| 183 | * 63:32 = wake time |
| 184 | * 31:0 = C-state for this core |
| 185 | */ |
| 186 | val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) | |
| 187 | ((uint64_t)state & MCE_SC7_ALLOWED_MASK); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 188 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 189 | /* issue command to check if SC7 is allowed */ |
| 190 | nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 191 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 192 | /* 1 = SC7 allowed, 0 = SC7 not allowed */ |
| 193 | ret = (nvg_get_result() != 0ULL) ? 1 : 0; |
| 194 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 195 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 196 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 197 | } |
| 198 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 199 | int32_t nvg_online_core(uint32_t ari_base, uint32_t core) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 200 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 201 | uint64_t cpu = read_mpidr() & (uint64_t)MPIDR_CPU_MASK; |
| 202 | uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & |
| 203 | (uint64_t)MIDR_IMPL_MASK; |
| 204 | int32_t ret = 0; |
| 205 | |
| 206 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 207 | |
| 208 | /* sanity check code id */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 209 | if ((core >= (uint32_t)MCE_CORE_ID_MAX) || (cpu == core)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 210 | ERROR("%s: unsupported core id (%d)\n", __func__, core); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 211 | ret = EINVAL; |
| 212 | } else { |
| 213 | /* |
| 214 | * The Denver cluster has 2 CPUs only - 0, 1. |
| 215 | */ |
| 216 | if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) { |
| 217 | ERROR("%s: unknown core id (%d)\n", __func__, core); |
| 218 | ret = EINVAL; |
| 219 | } else { |
| 220 | /* get a core online */ |
| 221 | nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, |
| 222 | ((uint64_t)core & MCE_CORE_ID_MASK)); |
| 223 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 224 | } |
| 225 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 226 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 227 | } |
| 228 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 229 | int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 230 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 231 | uint32_t val; |
| 232 | |
| 233 | (void)ari_base; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 234 | |
| 235 | /* |
| 236 | * If the enable bit is cleared, Auto-CC3 will be disabled by setting |
| 237 | * the SW visible voltage/frequency request registers for all non |
| 238 | * floorswept cores valid independent of StandbyWFI and disabling |
| 239 | * the IDLE voltage/frequency request register. If set, Auto-CC3 |
| 240 | * will be enabled by setting the ARM SW visible voltage/frequency |
| 241 | * request registers for all non floorswept cores to be enabled by |
| 242 | * StandbyWFI or the equivalent signal, and always keeping the IDLE |
| 243 | * voltage/frequency request register enabled. |
| 244 | */ |
| 245 | val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ |
| 246 | ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 247 | ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 248 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 249 | nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 250 | |
| 251 | return 0; |
| 252 | } |