blob: 0172b607ea36482a2fcfd600a11efe48aa6f309c [file] [log] [blame]
Achin Gupta191e86e2014-05-09 10:03:15 +01001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __INTERRUPT_MGMT_H__
32#define __INTERRUPT_MGMT_H__
33
34#include <arch.h>
35
36/*******************************************************************************
37 * Constants for the types of interrupts recognised by the IM framework
38 ******************************************************************************/
39#define INTR_TYPE_S_EL1 0
40#define INTR_TYPE_EL3 1
41#define INTR_TYPE_NS 2
42#define MAX_INTR_TYPES 3
43#define INTR_TYPE_INVAL MAX_INTR_TYPES
44/*
45 * Constant passed to the interrupt handler in the 'id' field when the
46 * framework does not read the gic registers to determine the interrupt id.
47 */
48#define INTR_ID_UNAVAILABLE 0xFFFFFFFF
49
50
51/*******************************************************************************
52 * Mask for _both_ the routing model bits in the 'flags' parameter and
53 * constants to define the valid routing models for each supported interrupt
54 * type
55 ******************************************************************************/
56#define INTR_RM_FLAGS_SHIFT 0x0
57#define INTR_RM_FLAGS_MASK 0x3
58/* Routed to EL3 from NS. Taken to S-EL1 from Secure */
59#define INTR_SEL1_VALID_RM0 0x2
60/* Routed to EL3 from NS and Secure */
61#define INTR_SEL1_VALID_RM1 0x3
62/* Routed to EL1/EL2 from NS and to S-EL1 from Secure */
63#define INTR_NS_VALID_RM0 0x0
64/* Routed to EL1/EL2 from NS and to EL3 from Secure */
65#define INTR_NS_VALID_RM1 0x1
Soby Mathew58e32d12015-11-23 13:58:45 +000066/* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */
67#define INTR_EL3_VALID_RM0 0x2
68/* Routed to EL3 from NS and Secure */
69#define INTR_EL3_VALID_RM1 0x3
Soby Mathew47903c02015-01-13 15:48:26 +000070/* This is the default routing model */
71#define INTR_DEFAULT_RM 0x0
Achin Gupta191e86e2014-05-09 10:03:15 +010072
73/*******************************************************************************
74 * Constants for the _individual_ routing model bits in the 'flags' field for
75 * each interrupt type and mask to validate the 'flags' parameter while
76 * registering an interrupt handler
77 ******************************************************************************/
78#define INTR_TYPE_FLAGS_MASK 0xFFFFFFFC
79
80#define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */
81#define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */
82#define INTR_RM_FROM_FLAG_MASK 1
83#define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \
84 & INTR_RM_FROM_FLAG_MASK)
85#define set_interrupt_rm_flag(flag, ss) (flag |= 1 << ss)
86#define clr_interrupt_rm_flag(flag, ss) (flag &= ~(1 << ss))
87
88
89/*******************************************************************************
90 * Macros to validate the routing model bits in the 'flags' for a type
91 * of interrupt. If the model does not match one of the valid masks
92 * -EINVAL is returned.
93 ******************************************************************************/
Soby Mathew58e32d12015-11-23 13:58:45 +000094#define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \
95 ((x) == INTR_SEL1_VALID_RM1 ? 0 :\
Achin Gupta191e86e2014-05-09 10:03:15 +010096 -EINVAL))
97
Soby Mathew58e32d12015-11-23 13:58:45 +000098#define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \
99 ((x) == INTR_NS_VALID_RM1 ? 0 :\
100 -EINVAL))
101
102#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \
103 ((x) == INTR_EL3_VALID_RM1 ? 0 :\
Achin Gupta191e86e2014-05-09 10:03:15 +0100104 -EINVAL))
105
106/*******************************************************************************
107 * Macros to set the 'flags' parameter passed to an interrupt type handler. Only
108 * the flag to indicate the security state when the exception was generated is
109 * supported.
110 ******************************************************************************/
111#define INTR_SRC_SS_FLAG_SHIFT 0 /* BIT[0] */
112#define INTR_SRC_SS_FLAG_MASK 1
113#define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT)
114#define clr_interrupt_src_ss(flag) (flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT))
115#define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \
116 INTR_SRC_SS_FLAG_MASK)
117
118#ifndef __ASSEMBLY__
119
120/* Prototype for defining a handler for an interrupt type */
121typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
122 uint32_t flags,
123 void *handle,
124 void *cookie);
125
126/*******************************************************************************
127 * Function & variable prototypes
128 ******************************************************************************/
Dan Handleya17fefa2014-05-14 12:38:32 +0100129uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
130int32_t set_routing_model(uint32_t type, uint32_t flags);
131int32_t register_interrupt_type_handler(uint32_t type,
132 interrupt_type_handler_t handler,
133 uint32_t flags);
134interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type);
Soby Mathew47903c02015-01-13 15:48:26 +0000135int disable_intr_rm_local(uint32_t type, uint32_t security_state);
136int enable_intr_rm_local(uint32_t type, uint32_t security_state);
Achin Gupta191e86e2014-05-09 10:03:15 +0100137
138#endif /*__ASSEMBLY__*/
139#endif /* __INTERRUPT_MGMT_H__ */