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Pritesh Raithatha9eb5db52017-01-02 19:42:31 +05301/*
Krishna Reddyae18d222017-12-07 13:52:39 -08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar07f970d2018-06-28 11:03:41 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +05306 */
7
Puneet Saxenacf8c0e22017-08-04 17:19:55 +05308#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <common/bl_common.h>
10
Steven Kaoa457f2e2017-11-14 18:52:05 +080011#include <mce.h>
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053012#include <memctrl_v2.h>
Puneet Saxenacf8c0e22017-08-04 17:19:55 +053013#include <tegra_mc_def.h>
Varun Wadekar07f970d2018-06-28 11:03:41 -070014#include <tegra186_private.h>
Puneet Saxenacf8c0e22017-08-04 17:19:55 +053015#include <tegra_platform.h>
Varun Wadekar07f970d2018-06-28 11:03:41 -070016#include <tegra_private.h>
17
18extern uint64_t tegra_bl31_phys_base;
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053019
20/*******************************************************************************
21 * Array to hold stream_id override config register offsets
22 ******************************************************************************/
23const static uint32_t tegra186_streamid_override_regs[] = {
24 MC_STREAMID_OVERRIDE_CFG_PTCR,
25 MC_STREAMID_OVERRIDE_CFG_AFIR,
26 MC_STREAMID_OVERRIDE_CFG_HDAR,
27 MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
28 MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
29 MC_STREAMID_OVERRIDE_CFG_SATAR,
30 MC_STREAMID_OVERRIDE_CFG_MPCORER,
31 MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
32 MC_STREAMID_OVERRIDE_CFG_AFIW,
33 MC_STREAMID_OVERRIDE_CFG_HDAW,
34 MC_STREAMID_OVERRIDE_CFG_MPCOREW,
35 MC_STREAMID_OVERRIDE_CFG_SATAW,
36 MC_STREAMID_OVERRIDE_CFG_ISPRA,
37 MC_STREAMID_OVERRIDE_CFG_ISPWA,
38 MC_STREAMID_OVERRIDE_CFG_ISPWB,
39 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
40 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
41 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
42 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
43 MC_STREAMID_OVERRIDE_CFG_TSECSRD,
44 MC_STREAMID_OVERRIDE_CFG_TSECSWR,
45 MC_STREAMID_OVERRIDE_CFG_GPUSRD,
46 MC_STREAMID_OVERRIDE_CFG_GPUSWR,
47 MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
48 MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
49 MC_STREAMID_OVERRIDE_CFG_SDMMCR,
50 MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
51 MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
52 MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
53 MC_STREAMID_OVERRIDE_CFG_SDMMCW,
54 MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
55 MC_STREAMID_OVERRIDE_CFG_VICSRD,
56 MC_STREAMID_OVERRIDE_CFG_VICSWR,
57 MC_STREAMID_OVERRIDE_CFG_VIW,
58 MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
59 MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
60 MC_STREAMID_OVERRIDE_CFG_APER,
61 MC_STREAMID_OVERRIDE_CFG_APEW,
62 MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
63 MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
64 MC_STREAMID_OVERRIDE_CFG_SESRD,
65 MC_STREAMID_OVERRIDE_CFG_SESWR,
66 MC_STREAMID_OVERRIDE_CFG_ETRR,
67 MC_STREAMID_OVERRIDE_CFG_ETRW,
68 MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
69 MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
70 MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
71 MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
72 MC_STREAMID_OVERRIDE_CFG_AXISR,
73 MC_STREAMID_OVERRIDE_CFG_AXISW,
74 MC_STREAMID_OVERRIDE_CFG_EQOSR,
75 MC_STREAMID_OVERRIDE_CFG_EQOSW,
76 MC_STREAMID_OVERRIDE_CFG_UFSHCR,
77 MC_STREAMID_OVERRIDE_CFG_UFSHCW,
78 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
79 MC_STREAMID_OVERRIDE_CFG_BPMPR,
80 MC_STREAMID_OVERRIDE_CFG_BPMPW,
81 MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
82 MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
83 MC_STREAMID_OVERRIDE_CFG_AONR,
84 MC_STREAMID_OVERRIDE_CFG_AONW,
85 MC_STREAMID_OVERRIDE_CFG_AONDMAR,
86 MC_STREAMID_OVERRIDE_CFG_AONDMAW,
87 MC_STREAMID_OVERRIDE_CFG_SCER,
88 MC_STREAMID_OVERRIDE_CFG_SCEW,
89 MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
90 MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
91 MC_STREAMID_OVERRIDE_CFG_APEDMAR,
92 MC_STREAMID_OVERRIDE_CFG_APEDMAW,
93 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
94 MC_STREAMID_OVERRIDE_CFG_VICSRD1,
95 MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
96};
97
98/*******************************************************************************
99 * Array to hold the security configs for stream IDs
100 ******************************************************************************/
101const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
Krishna Reddyae18d222017-12-07 13:52:39 -0800102 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530103 mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, DISABLE),
104 mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, DISABLE),
105 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530106 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530107 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
108 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
109 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530110 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530111 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
112 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530113 mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530114 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
115 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
116 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800117 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530118 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
119 mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, DISABLE),
120 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
121 mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE),
122 mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800123 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530124 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530125 mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530126 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800127 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530128 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530129 mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530130 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530131 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530132 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
133 mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530134 mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
135 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530136 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800137 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530138 mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530139 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530140 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800141 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530142 mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE),
143 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800144 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530145 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800146 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530147 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
148 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
149 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800150 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530151 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530152 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
153 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
154 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
155 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
156 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
157 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
158 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800159 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530160 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
161 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
162 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
163 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
164 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
165 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530166 mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha17fb18e2018-05-31 12:06:15 +0530167 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530168 mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
169 mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800170 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
171 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
172 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
173 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530174};
175
176/*******************************************************************************
177 * Array to hold the transaction override configs
178 ******************************************************************************/
179const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
180 mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
181 mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
182 mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
183 mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
184 mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
185 mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
186 mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
187 mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
188 mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
189 mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
190 mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
191 mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
192 mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
193 mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
194 mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
195 mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
196 mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
197 mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
198 mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
199 mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
200 mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
201 mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
202 mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
203 mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
204 mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
205 mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
206 mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
207 mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
208 mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
209 mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
210 mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
211};
212
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530213static void tegra186_memctrl_reconfig_mss_clients(void)
214{
215#if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
216 uint32_t val, wdata_0, wdata_1;
217
218 /*
219 * Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for
220 * boot and strongly ordered MSS clients to flush existing memory
221 * traffic and stall future requests.
222 */
223 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
224 assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
225
226 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530227 MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530228 MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
229 MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
230 MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
231 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
232
233 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
234 do {
235 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
236 } while ((val & wdata_0) != wdata_0);
237
238 /* Wait one more time due to SW WAR for known legacy issue */
239 do {
240 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
241 } while ((val & wdata_0) != wdata_0);
242
243 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
244 assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL);
245
246 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
247 MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
248 MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
249 MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
250 MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
251 MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
252 MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
253 MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
254 MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
255 MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB;
256 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
257
258 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
259 do {
260 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
261 } while ((val & wdata_1) != wdata_1);
262
263 /* Wait one more time due to SW WAR for known legacy issue */
264 do {
265 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
266 } while ((val & wdata_1) != wdata_1);
267
268 /*
269 * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
270 * strongly ordered MSS clients. ROC needs to be single point
271 * of control on overriding the memory type. So, remove TSA's
272 * memtype override.
273 *
274 * MC clients with default SO_DEV override still enabled at TSA:
275 * AONW, BPMPW, SCEW, APEW
276 */
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530277 mc_set_tsa_passthrough(AFIW);
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530278 mc_set_tsa_passthrough(HDAW);
279 mc_set_tsa_passthrough(SATAW);
280 mc_set_tsa_passthrough(XUSB_HOSTW);
281 mc_set_tsa_passthrough(XUSB_DEVW);
282 mc_set_tsa_passthrough(SDMMCWAB);
283 mc_set_tsa_passthrough(APEDMAW);
284 mc_set_tsa_passthrough(SESWR);
285 mc_set_tsa_passthrough(ETRW);
286 mc_set_tsa_passthrough(AXISW);
287 mc_set_tsa_passthrough(EQOSW);
288 mc_set_tsa_passthrough(UFSHCW);
289 mc_set_tsa_passthrough(BPMPDMAW);
290 mc_set_tsa_passthrough(AONDMAW);
291 mc_set_tsa_passthrough(SCEDMAW);
292
293 /* Parker has no IO Coherency support and need the following:
294 * Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB.
295 * ISO clients(DISP, VI, EQOS) should never snoop caches and
296 * don't need ROC/PCFIFO ordering.
297 * ISO clients(EQOS) that need ordering should use PCFIFO ordering
298 * and bypass ROC ordering by using FORCE_NON_COHERENT path.
299 * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
300 * over SMMU attributes.
301 * Force all Normal memory transactions from ISO and non-ISO to be
302 * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
303 * Force the SO_DEV transactions from ordered ISO clients(EQOS) to
304 * non-coherent path and enable MC PCFIFO interlock for ordering.
305 * Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
306 * XUSB, SATA) to coherent so that the transactions are
307 * ordered by ROC.
308 * PCFIFO ensure write ordering.
309 * Read after Write ordering is maintained/enforced by MC clients.
310 * Clients that need PCIe type write ordering must
311 * go through ROC ordering.
312 * Ordering enable for Read clients is not necessary.
313 * R5's and A9 would get necessary ordering from AXI and
314 * don't need ROC ordering enable:
315 * - MMIO ordering is through dev mapping and MMIO
316 * accesses bypass SMMU.
317 * - Normal memory is accessed through SMMU and ordering is
318 * ensured by client and AXI.
319 * - Ack point for Normal memory is WCAM in MC.
320 * - MMIO's can be early acked and AXI ensures dev memory ordering,
321 * Client ensures read/write direction change ordering.
322 * - See Bug 200312466 for more details.
323 *
324 * CGID_TAG_ADR is only present from T186 A02. As this code is common
325 * between A01 and A02, tegra_memctrl_set_overrides() programs
326 * CGID_TAG_ADR for the necessary clients on A02.
327 */
328 mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
329 mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
330 mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
331 mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
332 mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
333 mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
334 mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
335 mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
336 mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
337 mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
338 mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
339 mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
340 mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
341 mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
342 mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
343 /* See bug 200131110 comment #35*/
344 mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
345 mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
346 mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
347 mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
348 mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
349 mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
350 mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
351 mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
352 mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
353 mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
354 mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
355 mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
356 mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
357 mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
358 mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
359 mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
360 mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
361 mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
362 mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
363 /* See bug 200131110 comment #35*/
364 mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
365 mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
366 mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
367 mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
368 mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
369 mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
370 mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
371 mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
372 mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
373 mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
374 mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
375 mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
376 mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
377 mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
378 mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
379 mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
380 mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
381 mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
382 mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
383 mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
384 mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
385 mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
386 mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
387 mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
388 mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
389 mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
390 /* See bug 200131110 comment #35 */
391 mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
392 mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
393 mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
394 mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
395 mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
396 mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
397 mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
398 mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
399 mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
400 mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
401 /*
402 * See bug 200131110 comment #35 - there are no normal requests
403 * and AWID for SO/DEV requests is hardcoded in RTL for a
404 * particular PCIE controller
405 */
406 mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT);
407 mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
408
409 /*
410 * At this point, ordering can occur at ROC. So, remove PCFIFO's
411 * control over ordering requests.
412 *
413 * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
414 * boot and strongly ordered MSS clients
415 */
416 val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530417 mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530418 mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
419 mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
420 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
421
422 val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
423 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
424 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW);
425 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val);
426
427 val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
428 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB);
429 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val);
430
431 val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
432 mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
433 mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
434 mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
435 mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
436 mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
437 mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
438 mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
439 /* EQOSW is the only client that has PCFIFO order enabled. */
440 val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
441 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
442
443 val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
444 mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW);
445 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
446
447 /*
448 * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS
449 * clients to allow memory traffic from all clients to start passing
450 * through ROC
451 */
452 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
453 assert(val == wdata_0);
454
455 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
456 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
457
458 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
459 assert(val == wdata_1);
460
461 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
462 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
463
464#endif
465}
466
467static void tegra186_memctrl_set_overrides(void)
468{
469 const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
470 const mc_txn_override_cfg_t *mc_txn_override_cfgs;
471 uint32_t num_txn_override_cfgs;
472 uint32_t i, val;
473
474 /* Get the settings from the platform */
475 assert(plat_mc_settings != NULL);
476 mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
477 num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
478
479 /*
480 * Set the MC_TXN_OVERRIDE registers for write clients.
481 */
482 if ((tegra_chipid_is_t186()) &&
483 (!tegra_platform_is_silicon() ||
484 (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
485
486 /*
487 * GPU and NVENC settings for Tegra186 simulation and
488 * Silicon rev. A01
489 */
490 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
491 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
492 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
493 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
494
495 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
496 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
497 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
498 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
499
500 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
501 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
502 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
503 val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
504
505 } else {
506
507 /*
508 * Settings for Tegra186 silicon rev. A02 and onwards.
509 */
510 for (i = 0; i < num_txn_override_cfgs; i++) {
511 val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
512 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
513 tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
514 val | mc_txn_override_cfgs[i].cgid_tag);
515 }
516 }
517}
518
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530519/*******************************************************************************
520 * Struct to hold the memory controller settings
521 ******************************************************************************/
522static tegra_mc_settings_t tegra186_mc_settings = {
523 .streamid_override_cfg = tegra186_streamid_override_regs,
Anthony Zhou0e07e452017-07-26 17:16:54 +0800524 .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530525 .streamid_security_cfg = tegra186_streamid_sec_cfgs,
Anthony Zhou0e07e452017-07-26 17:16:54 +0800526 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530527 .txn_override_cfg = tegra186_txn_override_cfgs,
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530528 .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs),
529 .reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients,
530 .set_txn_overrides = tegra186_memctrl_set_overrides,
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530531};
532
533/*******************************************************************************
534 * Handler to return the pointer to the memory controller's settings struct
535 ******************************************************************************/
536tegra_mc_settings_t *tegra_get_mc_settings(void)
537{
538 return &tegra186_mc_settings;
539}
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700540
541/*******************************************************************************
542 * Handler to program the scratch registers with TZDRAM settings for the
543 * resume firmware
544 ******************************************************************************/
545void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
546{
547 uint32_t val;
Varun Wadekar07f970d2018-06-28 11:03:41 -0700548 uint64_t src_base_tzdram;
549 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
550 uint64_t src_len_in_bytes = BL31_END - BL31_START;
551
552 /* base address of BL3-1 source in TZDRAM */
553 src_base_tzdram = params_from_bl2->tzdram_base +
554 tegra186_get_cpu_reset_handler_size();
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700555
Steven Kaoa457f2e2017-11-14 18:52:05 +0800556 /*
557 * Setup the Memory controller to allow only secure accesses to
558 * the TZDRAM carveout
559 */
560 INFO("Configuring TrustZone DRAM Memory Carveout\n");
561
562 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
563 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
564 tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700565
566 /*
567 * When TZ encryption is enabled, we need to setup TZDRAM
568 * before CPU accesses TZ Carveout, else CPU will fetch
569 * non-decrypted data. So save TZDRAM setting for SC7 resume
570 * FW to restore.
571 *
572 * Scratch registers map:
573 * RSV55_0 = CFG1[12:0] | CFG0[31:20]
574 * RSV55_1 = CFG3[1:0]
575 */
576 val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
577 val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
Steven Kao186485e2017-10-23 18:22:09 +0800578 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_LO, val);
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700579
580 val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
Steven Kao186485e2017-10-23 18:22:09 +0800581 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);
Steven Kaoa457f2e2017-11-14 18:52:05 +0800582
583 /*
Varun Wadekar07f970d2018-06-28 11:03:41 -0700584 * save tzdram_addr_lo and ATF-size, this would be used in SC7-RF to
585 * generate SHA256.
586 */
587 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO,
588 (uint32_t)src_base_tzdram);
589 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI,
590 (uint32_t)src_len_in_bytes);
591
592 /*
Steven Kaoa457f2e2017-11-14 18:52:05 +0800593 * MCE propagates the security configuration values across the
594 * CCPLEX.
595 */
596 (void)mce_update_gsc_tzdram();
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700597}