blob: 85a12c55c43b099957f646ae5d1906e961924493 [file] [log] [blame]
Mikael Olsson7da66192021-02-12 17:30:22 +01001/*
Joshua Pimm6bc80672022-10-19 15:46:27 +01002 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Mikael Olsson7da66192021-02-12 17:30:22 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h>
8#include <stdbool.h>
9
10#include <common/debug.h>
11#include <common/runtime_svc.h>
12#include <drivers/arm/ethosn.h>
13#include <drivers/delay_timer.h>
14#include <lib/mmio.h>
Mikael Olsson3288b462022-08-15 17:12:58 +020015#include <lib/utils_def.h>
Mikael Olsson7da66192021-02-12 17:30:22 +010016#include <plat/arm/common/fconf_ethosn_getter.h>
17
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +010018#include <platform_def.h>
19
Mikael Olssona7df0d62023-01-13 09:56:41 +010020#if ARM_ETHOSN_NPU_TZMP1
21#include "ethosn_big_fw.h"
22#endif
23
Laurent Carlier5205df22021-09-16 15:10:35 +010024/*
Mikael Olsson3288b462022-08-15 17:12:58 +020025 * Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available
Laurent Carlier5205df22021-09-16 15:10:35 +010026 */
Mikael Olsson3288b462022-08-15 17:12:58 +020027#define ETHOSN_NUM_DEVICES \
28 FCONF_GET_PROPERTY(hw_config, ethosn_config, num_devices)
Mikael Olsson7da66192021-02-12 17:30:22 +010029
Mikael Olsson3288b462022-08-15 17:12:58 +020030#define ETHOSN_GET_DEVICE(dev_idx) \
31 FCONF_GET_PROPERTY(hw_config, ethosn_device, dev_idx)
Mikael Olsson7da66192021-02-12 17:30:22 +010032
33/* NPU core sec registry address */
34#define ETHOSN_CORE_SEC_REG(core_addr, reg_offset) \
35 (core_addr + reg_offset)
36
Mikael Olssond6cedcb2023-01-27 18:53:48 +010037#define ETHOSN_FW_VA_BASE 0x20000000UL
38#define ETHOSN_WORKING_DATA_VA_BASE 0x40000000UL
39#define ETHOSN_COMMAND_STREAM_VA_BASE 0x60000000UL
40
Mikael Olsson7da66192021-02-12 17:30:22 +010041/* Reset timeout in us */
42#define ETHOSN_RESET_TIMEOUT_US U(10 * 1000 * 1000)
43#define ETHOSN_RESET_WAIT_US U(1)
44
Mikael Olssonfe9677f2023-02-10 11:36:19 +010045#define ETHOSN_AUX_FEAT_LEVEL_IRQ U(0x1)
46#define ETHOSN_AUX_FEAT_STASHING U(0x2)
47
48#define SEC_AUXCTLR_REG U(0x0024)
49#define SEC_AUXCTLR_VAL U(0x80)
50#define SEC_AUXCTLR_LEVEL_IRQ_VAL U(0x04)
51#define SEC_AUXCTLR_STASHING_VAL U(0xA5000000)
52
Mikael Olsson7da66192021-02-12 17:30:22 +010053#define SEC_DEL_REG U(0x0004)
Mikael Olssonc7d3a272023-02-10 16:59:23 +010054#if ARM_ETHOSN_NPU_TZMP1
55#define SEC_DEL_VAL U(0x808)
56#else
Mikael Olssonfe9677f2023-02-10 11:36:19 +010057#define SEC_DEL_VAL U(0x80C)
Mikael Olssonc7d3a272023-02-10 16:59:23 +010058#endif
Mikael Olsson7da66192021-02-12 17:30:22 +010059#define SEC_DEL_EXCC_MASK U(0x20)
60
61#define SEC_SECCTLR_REG U(0x0010)
Mikael Olssonbfd9da72023-01-11 10:36:22 +010062/* Set bit[10] = 1 to workaround erratum 2838783 */
63#define SEC_SECCTLR_VAL U(0x403)
Mikael Olsson7da66192021-02-12 17:30:22 +010064
Mikael Olssondf0bb042023-02-10 16:59:03 +010065#define SEC_DEL_ADDR_EXT_REG U(0x201C)
66#define SEC_DEL_ADDR_EXT_VAL U(0x1)
Mikael Olsson7da66192021-02-12 17:30:22 +010067
68#define SEC_SYSCTRL0_REG U(0x0018)
Mikael Olssonc7d3a272023-02-10 16:59:23 +010069#define SEC_SYSCTRL0_CPU_WAIT U(1)
Mikael Olsson47675f22022-11-04 15:01:02 +010070#define SEC_SYSCTRL0_SLEEPING U(1U << 4)
Mikael Olssonc7d3a272023-02-10 16:59:23 +010071#define SEC_SYSCTRL0_INITVTOR_MASK U(0x1FFFFF80)
Mikael Olsson7da66192021-02-12 17:30:22 +010072#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
73#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
74
Mikael Olssonfe9677f2023-02-10 11:36:19 +010075#define SEC_SYSCTRL1_REG U(0x001C)
76#define SEC_SYSCTRL1_VAL U(0x180110)
77
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +010078#define SEC_NSAID_REG_BASE U(0x3004)
79#define SEC_NSAID_OFFSET U(0x1000)
80
Mikael Olsson3288b462022-08-15 17:12:58 +020081#define SEC_MMUSID_REG_BASE U(0x3008)
82#define SEC_MMUSID_OFFSET U(0x1000)
83
Mikael Olssondf0bb042023-02-10 16:59:03 +010084#define SEC_ADDR_EXT_REG_BASE U(0x3018)
85#define SEC_ADDR_EXT_OFFSET U(0x1000)
86#define SEC_ADDR_EXT_SHIFT U(0x14)
87#define SEC_ADDR_EXT_MASK U(0x1FFFFE00)
88
89#define SEC_ATTR_CTLR_REG_BASE U(0x3010)
90#define SEC_ATTR_CTLR_OFFSET U(0x1000)
91#define SEC_ATTR_CTLR_NUM U(9)
92#define SEC_ATTR_CTLR_VAL U(0x1)
93
Mikael Olssona7df0d62023-01-13 09:56:41 +010094#define SEC_NPU_ID_REG U(0xF000)
95#define SEC_NPU_ID_ARCH_VER_SHIFT U(0X10)
96
Mikael Olsson80b61f52023-03-14 18:29:06 +010097#define FIRMWARE_STREAM_INDEX U(0x0)
98#define WORKING_STREAM_INDEX U(0x1)
Mikael Olssonc7d3a272023-02-10 16:59:23 +010099#define PLE_STREAM_INDEX U(0x4)
Mikael Olsson80b61f52023-03-14 18:29:06 +0100100#define INPUT_STREAM_INDEX U(0x6)
101#define INTERMEDIATE_STREAM_INDEX U(0x7)
102#define OUTPUT_STREAM_INDEX U(0x8)
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100103
Mikael Olssondf0bb042023-02-10 16:59:03 +0100104#define TO_EXTEND_ADDR(addr) \
105 ((addr >> SEC_ADDR_EXT_SHIFT) & SEC_ADDR_EXT_MASK)
106
Mikael Olssona7df0d62023-01-13 09:56:41 +0100107#if ARM_ETHOSN_NPU_TZMP1
108CASSERT(ARM_ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base);
109static const struct ethosn_big_fw *big_fw;
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100110
111#define FW_INITVTOR_ADDR(big_fw) \
112 ((ETHOSN_FW_VA_BASE + big_fw->vector_table_offset) & \
113 SEC_SYSCTRL0_INITVTOR_MASK)
114
115#define SYSCTRL0_INITVTOR_ADDR(value) \
116 (value & SEC_SYSCTRL0_INITVTOR_MASK)
117
Mikael Olssona7df0d62023-01-13 09:56:41 +0100118#endif
119
Mikael Olsson3288b462022-08-15 17:12:58 +0200120static bool ethosn_get_device_and_core(uintptr_t core_addr,
121 const struct ethosn_device_t **dev_match,
122 const struct ethosn_core_t **core_match)
Laurent Carlier5205df22021-09-16 15:10:35 +0100123{
Mikael Olsson3288b462022-08-15 17:12:58 +0200124 uint32_t dev_idx;
125 uint32_t core_idx;
126
127 for (dev_idx = 0U; dev_idx < ETHOSN_NUM_DEVICES; ++dev_idx) {
128 const struct ethosn_device_t *dev = ETHOSN_GET_DEVICE(dev_idx);
129
130 for (core_idx = 0U; core_idx < dev->num_cores; ++core_idx) {
131 const struct ethosn_core_t *core = &(dev->cores[core_idx]);
132
133 if (core->addr == core_addr) {
134 *dev_match = dev;
135 *core_match = core;
136 return true;
137 }
Laurent Carlier5205df22021-09-16 15:10:35 +0100138 }
139 }
140
Mikael Olsson3288b462022-08-15 17:12:58 +0200141 WARN("ETHOSN: Unknown core address given to SMC call.\n");
Laurent Carlier5205df22021-09-16 15:10:35 +0100142 return false;
143}
144
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100145#if ARM_ETHOSN_NPU_TZMP1
Mikael Olssona7df0d62023-01-13 09:56:41 +0100146static uint32_t ethosn_core_read_arch_version(uintptr_t core_addr)
147{
148 uint32_t npu_id = mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr,
149 SEC_NPU_ID_REG));
150
151 return (npu_id >> SEC_NPU_ID_ARCH_VER_SHIFT);
152}
153
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100154static void ethosn_configure_stream_nsaid(const struct ethosn_core_t *core,
155 bool is_protected)
156{
157 size_t i;
Mikael Olsson80b61f52023-03-14 18:29:06 +0100158 uint32_t streams[9] = {[0 ... 8] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID};
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100159
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100160 streams[FIRMWARE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
161 streams[PLE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID;
162
Mikael Olsson80b61f52023-03-14 18:29:06 +0100163 streams[WORKING_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
164
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100165 if (is_protected) {
Mikael Olsson80b61f52023-03-14 18:29:06 +0100166 streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID;
167 streams[INTERMEDIATE_STREAM_INDEX] =
168 ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
169 streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID;
170 } else {
171 streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID;
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100172 streams[INTERMEDIATE_STREAM_INDEX] =
Mikael Olsson80b61f52023-03-14 18:29:06 +0100173 ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
174 streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID;
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100175 }
176
177 for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
178 const uintptr_t reg_addr = SEC_NSAID_REG_BASE +
179 (SEC_NSAID_OFFSET * i);
180 mmio_write_32(ETHOSN_CORE_SEC_REG(core->addr, reg_addr),
181 streams[i]);
182 }
183}
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100184
185static void ethosn_configure_vector_table(uintptr_t core_addr)
186{
187 mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG),
188 FW_INITVTOR_ADDR(big_fw));
189}
190
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100191#endif
192
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100193static void ethosn_configure_events(uintptr_t core_addr)
194{
195 mmio_write_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL1_REG), SEC_SYSCTRL1_VAL);
196}
197
198static bool ethosn_configure_aux_features(const struct ethosn_device_t *device,
199 uintptr_t core_addr,
200 uint32_t features)
201{
202 uint32_t val = SEC_AUXCTLR_VAL;
203
204 if (features & ETHOSN_AUX_FEAT_LEVEL_IRQ) {
205 val |= SEC_AUXCTLR_LEVEL_IRQ_VAL;
206 }
207
208 if (features & ETHOSN_AUX_FEAT_STASHING) {
209 /* Stashing can't be used with reserved memory */
210 if (device->has_reserved_memory) {
211 return false;
212 }
213
214 val |= SEC_AUXCTLR_STASHING_VAL;
215 }
216
217 mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_AUXCTLR_REG), val);
218
219 return true;
220}
221
Mikael Olsson3288b462022-08-15 17:12:58 +0200222static void ethosn_configure_smmu_streams(const struct ethosn_device_t *device,
223 const struct ethosn_core_t *core,
224 uint32_t asset_alloc_idx)
225{
226 const struct ethosn_main_allocator_t *main_alloc =
227 &(core->main_allocator);
228 const struct ethosn_asset_allocator_t *asset_alloc =
229 &(device->asset_allocators[asset_alloc_idx]);
230 const uint32_t streams[9] = {
231 main_alloc->firmware.stream_id,
232 main_alloc->working_data.stream_id,
233 asset_alloc->command_stream.stream_id,
234 0U, /* Not used*/
235 main_alloc->firmware.stream_id,
236 asset_alloc->weight_data.stream_id,
237 asset_alloc->buffer_data.stream_id,
238 asset_alloc->intermediate_data.stream_id,
239 asset_alloc->buffer_data.stream_id
240 };
241 size_t i;
242
243 for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
244 const uintptr_t reg_addr = SEC_MMUSID_REG_BASE +
245 (SEC_MMUSID_OFFSET * i);
246 mmio_write_32(ETHOSN_CORE_SEC_REG(core->addr, reg_addr),
247 streams[i]);
248 }
249}
250
Mikael Olssondf0bb042023-02-10 16:59:03 +0100251static void ethosn_configure_stream_addr_extends(const struct ethosn_device_t *device,
252 uintptr_t core_addr)
253{
254 uint32_t addr_extends[3] = { 0 };
255 size_t i;
256
257 if (device->has_reserved_memory) {
258 const uint32_t addr = TO_EXTEND_ADDR(device->reserved_memory_addr);
259
260 addr_extends[0] = addr;
261 addr_extends[1] = addr;
262 addr_extends[2] = addr;
263 } else {
264 addr_extends[0] = TO_EXTEND_ADDR(ETHOSN_FW_VA_BASE);
265 addr_extends[1] = TO_EXTEND_ADDR(ETHOSN_WORKING_DATA_VA_BASE);
266 addr_extends[2] = TO_EXTEND_ADDR(ETHOSN_COMMAND_STREAM_VA_BASE);
267 }
268
269 for (i = 0U; i < ARRAY_SIZE(addr_extends); ++i) {
270 const uintptr_t reg_addr = SEC_ADDR_EXT_REG_BASE +
271 (SEC_ADDR_EXT_OFFSET * i);
272 mmio_write_32(ETHOSN_CORE_SEC_REG(core_addr, reg_addr),
273 addr_extends[i]);
274 }
275}
276
277static void ethosn_configure_stream_attr_ctlr(uintptr_t core_addr)
278{
279 size_t i;
280
281 for (i = 0U; i < SEC_ATTR_CTLR_NUM; ++i) {
282 const uintptr_t reg_addr = SEC_ATTR_CTLR_REG_BASE +
283 (SEC_ATTR_CTLR_OFFSET * i);
284 mmio_write_32(ETHOSN_CORE_SEC_REG(core_addr, reg_addr),
285 SEC_ATTR_CTLR_VAL);
286 }
287}
288
Mikael Olsson7da66192021-02-12 17:30:22 +0100289static void ethosn_delegate_to_ns(uintptr_t core_addr)
290{
291 mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG),
292 SEC_SECCTLR_VAL);
293
294 mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG),
295 SEC_DEL_VAL);
296
Mikael Olsson7da66192021-02-12 17:30:22 +0100297 mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_ADDR_EXT_REG),
298 SEC_DEL_ADDR_EXT_VAL);
299}
300
Laurent Carlier5205df22021-09-16 15:10:35 +0100301static int ethosn_is_sec(uintptr_t core_addr)
Mikael Olsson7da66192021-02-12 17:30:22 +0100302{
Laurent Carlier5205df22021-09-16 15:10:35 +0100303 if ((mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG))
Mikael Olsson7da66192021-02-12 17:30:22 +0100304 & SEC_DEL_EXCC_MASK) != 0U) {
305 return 0;
306 }
307
308 return 1;
309}
310
Mikael Olsson47675f22022-11-04 15:01:02 +0100311static int ethosn_core_is_sleeping(uintptr_t core_addr)
312{
313 const uintptr_t sysctrl0_reg =
314 ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
315 const uint32_t sleeping_mask = SEC_SYSCTRL0_SLEEPING;
316
317 return ((mmio_read_32(sysctrl0_reg) & sleeping_mask) == sleeping_mask);
318}
319
Mikael Olssonf6638032023-01-27 18:26:36 +0100320static bool ethosn_core_reset(uintptr_t core_addr, bool hard_reset)
Mikael Olsson7da66192021-02-12 17:30:22 +0100321{
322 unsigned int timeout;
323 const uintptr_t sysctrl0_reg =
324 ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
Mikael Olssonf6638032023-01-27 18:26:36 +0100325 const uint32_t reset_val = hard_reset ? SEC_SYSCTRL0_HARD_RESET :
326 SEC_SYSCTRL0_SOFT_RESET;
Mikael Olsson7da66192021-02-12 17:30:22 +0100327
328 mmio_write_32(sysctrl0_reg, reset_val);
329
330 /* Wait for reset to complete */
331 for (timeout = 0U; timeout < ETHOSN_RESET_TIMEOUT_US;
332 timeout += ETHOSN_RESET_WAIT_US) {
333
334 if ((mmio_read_32(sysctrl0_reg) & reset_val) == 0U) {
335 break;
336 }
337
338 udelay(ETHOSN_RESET_WAIT_US);
339 }
340
341 return timeout < ETHOSN_RESET_TIMEOUT_US;
342}
343
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100344static int ethosn_core_boot_fw(uintptr_t core_addr)
345{
346#if ARM_ETHOSN_NPU_TZMP1
347 const uintptr_t sysctrl0_reg = ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
348 const uint32_t sysctrl0_val = mmio_read_32(sysctrl0_reg);
349 const bool waiting = (sysctrl0_val & SEC_SYSCTRL0_CPU_WAIT);
350
351 if (!waiting) {
352 WARN("ETHOSN: Firmware is already running.\n");
353 return ETHOSN_INVALID_STATE;
354 }
355
356 if (SYSCTRL0_INITVTOR_ADDR(sysctrl0_val) != FW_INITVTOR_ADDR(big_fw)) {
357 WARN("ETHOSN: Unknown vector table won't boot firmware.\n");
358 return ETHOSN_INVALID_CONFIGURATION;
359 }
360
361 mmio_clrbits_32(sysctrl0_reg, SEC_SYSCTRL0_CPU_WAIT);
362
363 return ETHOSN_SUCCESS;
364#else
365 return ETHOSN_NOT_SUPPORTED;
366#endif
367}
368
Mikael Olssonf6638032023-01-27 18:26:36 +0100369static int ethosn_core_full_reset(const struct ethosn_device_t *device,
370 const struct ethosn_core_t *core,
371 bool hard_reset,
372 u_register_t asset_alloc_idx,
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100373 u_register_t is_protected,
374 u_register_t aux_features)
Mikael Olsson7da66192021-02-12 17:30:22 +0100375{
Mikael Olssonf6638032023-01-27 18:26:36 +0100376 if (!device->has_reserved_memory &&
377 asset_alloc_idx >= device->num_allocators) {
378 WARN("ETHOSN: Unknown asset allocator index given to SMC call.\n");
379 return ETHOSN_UNKNOWN_ALLOCATOR_IDX;
Mikael Olsson7da66192021-02-12 17:30:22 +0100380 }
381
Mikael Olssonf6638032023-01-27 18:26:36 +0100382 if (!ethosn_core_reset(core->addr, hard_reset)) {
383 return ETHOSN_FAILURE;
Mikael Olsson7da66192021-02-12 17:30:22 +0100384 }
385
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100386 if (!ethosn_configure_aux_features(device, core->addr, aux_features)) {
387 return ETHOSN_INVALID_CONFIGURATION;
388 }
389
390 ethosn_configure_events(core->addr);
391
Mikael Olssonf6638032023-01-27 18:26:36 +0100392 if (!device->has_reserved_memory) {
393 ethosn_configure_smmu_streams(device, core, asset_alloc_idx);
394
395#if ARM_ETHOSN_NPU_TZMP1
396 ethosn_configure_stream_nsaid(core, is_protected);
397#endif
Mikael Olsson7da66192021-02-12 17:30:22 +0100398 }
399
Mikael Olssondf0bb042023-02-10 16:59:03 +0100400 ethosn_configure_stream_addr_extends(device, core->addr);
401 ethosn_configure_stream_attr_ctlr(core->addr);
402
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100403#if ARM_ETHOSN_NPU_TZMP1
404 ethosn_configure_vector_table(core->addr);
405#endif
406
Mikael Olssonf6638032023-01-27 18:26:36 +0100407 ethosn_delegate_to_ns(core->addr);
408
409 return ETHOSN_SUCCESS;
410}
411
412static uintptr_t ethosn_smc_core_reset_handler(const struct ethosn_device_t *device,
413 const struct ethosn_core_t *core,
414 bool hard_reset,
415 u_register_t asset_alloc_idx,
416 u_register_t reset_type,
417 u_register_t is_protected,
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100418 u_register_t aux_features,
Mikael Olssonf6638032023-01-27 18:26:36 +0100419 void *handle)
420{
421 int ret;
422
423 switch (reset_type) {
424 case ETHOSN_RESET_TYPE_FULL:
425 ret = ethosn_core_full_reset(device, core, hard_reset,
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100426 asset_alloc_idx, is_protected,
427 aux_features);
Mikael Olssonf6638032023-01-27 18:26:36 +0100428 break;
429 case ETHOSN_RESET_TYPE_HALT:
430 ret = ethosn_core_reset(core->addr, hard_reset) ? ETHOSN_SUCCESS : ETHOSN_FAILURE;
431 break;
432 default:
433 WARN("ETHOSN: Invalid reset type given to SMC call.\n");
434 ret = ETHOSN_INVALID_PARAMETER;
435 break;
Laurent Carlier5205df22021-09-16 15:10:35 +0100436 }
437
Mikael Olssonf6638032023-01-27 18:26:36 +0100438 SMC_RET1(handle, ret);
439}
440
441static uintptr_t ethosn_smc_core_handler(uint32_t fid,
442 u_register_t core_addr,
443 u_register_t asset_alloc_idx,
444 u_register_t reset_type,
445 u_register_t is_protected,
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100446 u_register_t aux_features,
Mikael Olssonf6638032023-01-27 18:26:36 +0100447 void *handle)
448{
449 bool hard_reset = false;
450 const struct ethosn_device_t *device = NULL;
451 const struct ethosn_core_t *core = NULL;
452
Mikael Olsson3288b462022-08-15 17:12:58 +0200453 if (!ethosn_get_device_and_core(core_addr, &device, &core)) {
Laurent Carlier5205df22021-09-16 15:10:35 +0100454 SMC_RET1(handle, ETHOSN_UNKNOWN_CORE_ADDRESS);
455 }
456
Laurent Carlier5205df22021-09-16 15:10:35 +0100457 switch (fid) {
Mikael Olsson7da66192021-02-12 17:30:22 +0100458 case ETHOSN_FNUM_IS_SEC:
Mikael Olsson3288b462022-08-15 17:12:58 +0200459 SMC_RET1(handle, ethosn_is_sec(core->addr));
Mikael Olsson47675f22022-11-04 15:01:02 +0100460 case ETHOSN_FNUM_IS_SLEEPING:
461 SMC_RET1(handle, ethosn_core_is_sleeping(core->addr));
Mikael Olsson7da66192021-02-12 17:30:22 +0100462 case ETHOSN_FNUM_HARD_RESET:
Mikael Olssonf6638032023-01-27 18:26:36 +0100463 hard_reset = true;
Mikael Olsson7da66192021-02-12 17:30:22 +0100464 /* Fallthrough */
465 case ETHOSN_FNUM_SOFT_RESET:
Mikael Olssonf6638032023-01-27 18:26:36 +0100466 return ethosn_smc_core_reset_handler(device, core,
467 hard_reset,
468 asset_alloc_idx,
469 reset_type,
470 is_protected,
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100471 aux_features,
Mikael Olssonf6638032023-01-27 18:26:36 +0100472 handle);
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100473 case ETHOSN_FNUM_BOOT_FW:
474 SMC_RET1(handle, ethosn_core_boot_fw(core->addr));
Mikael Olssonf6638032023-01-27 18:26:36 +0100475 default:
476 WARN("ETHOSN: Unimplemented SMC call: 0x%x\n", fid);
477 SMC_RET1(handle, SMC_UNK);
478 }
479}
480
Mikael Olssond6cedcb2023-01-27 18:53:48 +0100481static uintptr_t ethosn_smc_fw_prop_handler(u_register_t fw_property,
482 void *handle)
483{
484#if ARM_ETHOSN_NPU_TZMP1
485 switch (fw_property) {
486 case ETHOSN_FW_PROP_VERSION:
487 SMC_RET4(handle, ETHOSN_SUCCESS,
488 big_fw->fw_ver_major,
489 big_fw->fw_ver_minor,
490 big_fw->fw_ver_patch);
491 case ETHOSN_FW_PROP_MEM_INFO:
492 SMC_RET3(handle, ETHOSN_SUCCESS,
493 ((void *)big_fw) + big_fw->offset,
494 big_fw->size);
495 case ETHOSN_FW_PROP_OFFSETS:
496 SMC_RET3(handle, ETHOSN_SUCCESS,
497 big_fw->ple_offset,
498 big_fw->unpriv_stack_offset);
499 case ETHOSN_FW_PROP_VA_MAP:
500 SMC_RET4(handle, ETHOSN_SUCCESS,
501 ETHOSN_FW_VA_BASE,
502 ETHOSN_WORKING_DATA_VA_BASE,
503 ETHOSN_COMMAND_STREAM_VA_BASE);
504 default:
505 WARN("ETHOSN: Unknown firmware property\n");
506 SMC_RET1(handle, ETHOSN_INVALID_PARAMETER);
507 }
508#else
509 SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
510#endif
511}
512
Mikael Olssonf6638032023-01-27 18:26:36 +0100513uintptr_t ethosn_smc_handler(uint32_t smc_fid,
514 u_register_t x1,
515 u_register_t x2,
516 u_register_t x3,
517 u_register_t x4,
518 void *cookie,
519 void *handle,
520 u_register_t flags)
521{
522 const uint32_t fid = smc_fid & FUNCID_NUM_MASK;
Mikael Olsson3288b462022-08-15 17:12:58 +0200523
Mikael Olssonf6638032023-01-27 18:26:36 +0100524 /* Only SiP fast calls are expected */
525 if ((GET_SMC_TYPE(smc_fid) != SMC_TYPE_FAST) ||
526 (GET_SMC_OEN(smc_fid) != OEN_SIP_START)) {
527 SMC_RET1(handle, SMC_UNK);
528 }
Rajasekaran Kalidossf8a18b82022-11-16 17:16:44 +0100529
Mikael Olssonf6638032023-01-27 18:26:36 +0100530 /* Truncate parameters to 32-bits for SMC32 */
531 if (GET_SMC_CC(smc_fid) == SMC_32) {
532 x1 &= 0xFFFFFFFF;
533 x2 &= 0xFFFFFFFF;
534 x3 &= 0xFFFFFFFF;
535 x4 &= 0xFFFFFFFF;
536 }
Mikael Olsson3288b462022-08-15 17:12:58 +0200537
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100538 if (!is_ethosn_fid(smc_fid) || (fid > ETHOSN_FNUM_BOOT_FW)) {
Mikael Olssonf6638032023-01-27 18:26:36 +0100539 WARN("ETHOSN: Unknown SMC call: 0x%x\n", smc_fid);
Mikael Olsson7da66192021-02-12 17:30:22 +0100540 SMC_RET1(handle, SMC_UNK);
541 }
Mikael Olssonf6638032023-01-27 18:26:36 +0100542
Mikael Olssond6cedcb2023-01-27 18:53:48 +0100543 switch (fid) {
544 case ETHOSN_FNUM_VERSION:
Mikael Olssonf6638032023-01-27 18:26:36 +0100545 SMC_RET2(handle, ETHOSN_VERSION_MAJOR, ETHOSN_VERSION_MINOR);
Mikael Olssond6cedcb2023-01-27 18:53:48 +0100546 case ETHOSN_FNUM_GET_FW_PROP:
547 return ethosn_smc_fw_prop_handler(x1, handle);
Mikael Olssonf6638032023-01-27 18:26:36 +0100548 }
549
Mikael Olssonfe9677f2023-02-10 11:36:19 +0100550 return ethosn_smc_core_handler(fid, x1, x2, x3, x4,
551 SMC_GET_GP(handle, CTX_GPREG_X5),
552 handle);
Mikael Olsson7da66192021-02-12 17:30:22 +0100553}
Mikael Olsson461bf7d2023-01-18 18:05:15 +0100554
555int ethosn_smc_setup(void)
556{
Mikael Olssona7df0d62023-01-13 09:56:41 +0100557#if ARM_ETHOSN_NPU_TZMP1
558 struct ethosn_device_t *dev;
559 uint32_t arch_ver;
560#endif
561
Mikael Olsson461bf7d2023-01-18 18:05:15 +0100562 if (ETHOSN_NUM_DEVICES == 0U) {
563 ERROR("ETHOSN: No NPU found\n");
564 return ETHOSN_FAILURE;
565 }
566
Mikael Olssona7df0d62023-01-13 09:56:41 +0100567#if ARM_ETHOSN_NPU_TZMP1
568
569 /* Only one NPU core is supported in the TZMP1 setup */
570 if ((ETHOSN_NUM_DEVICES != 1U) ||
571 (ETHOSN_GET_DEVICE(0U)->num_cores != 1U)) {
572 ERROR("ETHOSN: TZMP1 doesn't support multiple NPU cores\n");
573 return ETHOSN_FAILURE;
574 }
575
576 dev = ETHOSN_GET_DEVICE(0U);
Mikael Olssonc7d3a272023-02-10 16:59:23 +0100577 if (dev->has_reserved_memory) {
578 ERROR("ETHOSN: TZMP1 doesn't support using reserved memory\n");
579 return ETHOSN_FAILURE;
580 }
581
Mikael Olssona7df0d62023-01-13 09:56:41 +0100582 arch_ver = ethosn_core_read_arch_version(dev->cores[0U].addr);
583 big_fw = (struct ethosn_big_fw *)ARM_ETHOSN_NPU_FW_IMAGE_BASE;
584
585 if (!ethosn_big_fw_verify_header(big_fw, arch_ver)) {
586 return ETHOSN_FAILURE;
587 }
588
589 NOTICE("ETHOSN: TZMP1 setup succeeded with firmware version %u.%u.%u\n",
590 big_fw->fw_ver_major, big_fw->fw_ver_minor,
591 big_fw->fw_ver_patch);
592#else
593 NOTICE("ETHOSN: Setup succeeded\n");
594#endif
595
Mikael Olsson461bf7d2023-01-18 18:05:15 +0100596 return 0;
597}