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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Deepika Bhavnani6bd46662019-08-15 00:56:46 +03002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <string.h>
9
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <common/bl_common.h>
13#include <common/debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <lib/el3_runtime/context_mgmt.h>
16#include <lib/utils.h>
17#include <plat/common/platform.h>
18
Dan Handley714a0d22014-04-09 13:13:04 +010019#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Achin Gupta607084e2014-02-09 18:24:19 +000021/*
Jeenu Viswambharan7f366602014-02-20 17:11:00 +000022 * SPD power management operations, expected to be supplied by the registered
23 * SPD on successful SP initialization
Achin Gupta607084e2014-02-09 18:24:19 +000024 */
Dan Handleye2712bc2014-04-10 15:37:22 +010025const spd_pm_ops_t *psci_spd_pm;
Achin Gupta607084e2014-02-09 18:24:19 +000026
Soby Mathew981487a2015-07-13 14:10:57 +010027/*
28 * PSCI requested local power state map. This array is used to store the local
29 * power states requested by a CPU for power levels from level 1 to
30 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power
31 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a
32 * CPU are the same.
33 *
34 * During state coordination, the platform is passed an array containing the
35 * local states requested for a particular non cpu power domain by each cpu
36 * within the domain.
37 *
38 * TODO: Dense packing of the requested states will cause cache thrashing
39 * when multiple power domains write to it. If we allocate the requested
40 * states at each power level in a cache-line aligned per-domain memory,
41 * the cache thrashing can be avoided.
42 */
43static plat_local_state_t
44 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
45
46
Achin Gupta4f6ad662013-10-25 09:08:21 +010047/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010048 * Arrays that hold the platform's power domain tree information for state
49 * management of power domains.
50 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain
51 * which is an ancestor of a CPU power domain.
52 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain
Achin Gupta4f6ad662013-10-25 09:08:21 +010053 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010054non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]
Soby Mathew2ae20432015-01-08 18:02:44 +000055#if USE_COHERENT_MEM
Soren Brinkmann46dd1702016-01-14 10:11:05 -080056__section("tzfw_coherent_mem")
Soby Mathew2ae20432015-01-08 18:02:44 +000057#endif
58;
Achin Gupta4f6ad662013-10-25 09:08:21 +010059
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +000060/* Lock for PSCI state coordination */
61DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +010062
Soby Mathew981487a2015-07-13 14:10:57 +010063cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
64
Achin Gupta4f6ad662013-10-25 09:08:21 +010065/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010066 * Pointer to functions exported by the platform to complete power mgmt. ops
67 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +010068const plat_psci_ops_t *psci_plat_pm_ops;
Achin Gupta4f6ad662013-10-25 09:08:21 +010069
Soby Mathew981487a2015-07-13 14:10:57 +010070/******************************************************************************
71 * Check that the maximum power level supported by the platform makes sense
72 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010073CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
74 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
75 assert_platform_max_pwrlvl_check);
Soby Mathew2b7de2b2015-02-12 14:45:02 +000076
Soby Mathew981487a2015-07-13 14:10:57 +010077/*
78 * The plat_local_state used by the platform is one of these types: RUN,
79 * RETENTION and OFF. The platform can define further sub-states for each type
80 * apart from RUN. This categorization is done to verify the sanity of the
81 * psci_power_state passed by the platform and to print debug information. The
82 * categorization is done on the basis of the following conditions:
83 *
84 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN.
85 *
86 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is
87 * STATE_TYPE_RETN.
88 *
89 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is
90 * STATE_TYPE_OFF.
91 */
92typedef enum plat_local_state_type {
93 STATE_TYPE_RUN = 0,
94 STATE_TYPE_RETN,
95 STATE_TYPE_OFF
96} plat_local_state_type_t;
97
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010098/* Function used to categorize plat_local_state. */
99static plat_local_state_type_t find_local_state_type(plat_local_state_t state)
100{
101 if (state != 0U) {
102 if (state > PLAT_MAX_RET_STATE) {
103 return STATE_TYPE_OFF;
104 } else {
105 return STATE_TYPE_RETN;
106 }
107 } else {
108 return STATE_TYPE_RUN;
109 }
110}
Soby Mathew981487a2015-07-13 14:10:57 +0100111
112/******************************************************************************
113 * Check that the maximum retention level supported by the platform is less
114 * than the maximum off level.
115 *****************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100116CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE,
Soby Mathew981487a2015-07-13 14:10:57 +0100117 assert_platform_max_off_and_retn_state_check);
118
119/******************************************************************************
120 * This function ensures that the power state parameter in a CPU_SUSPEND request
121 * is valid. If so, it returns the requested states for each power level.
122 *****************************************************************************/
123int psci_validate_power_state(unsigned int power_state,
124 psci_power_state_t *state_info)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100125{
Soby Mathew981487a2015-07-13 14:10:57 +0100126 /* Check SBZ bits in power state are zero */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100127 if (psci_check_power_state(power_state) != 0U)
Soby Mathew981487a2015-07-13 14:10:57 +0100128 return PSCI_E_INVALID_PARAMS;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100129
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100130 assert(psci_plat_pm_ops->validate_power_state != NULL);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100131
Soby Mathew981487a2015-07-13 14:10:57 +0100132 /* Validate the power_state using platform pm_ops */
133 return psci_plat_pm_ops->validate_power_state(power_state, state_info);
134}
Achin Guptaf6b9e992014-07-31 11:19:11 +0100135
Soby Mathew981487a2015-07-13 14:10:57 +0100136/******************************************************************************
137 * This function retrieves the `psci_power_state_t` for system suspend from
138 * the platform.
139 *****************************************************************************/
140void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info)
141{
142 /*
143 * Assert that the required pm_ops hook is implemented to ensure that
144 * the capability detected during psci_setup() is valid.
145 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100146 assert(psci_plat_pm_ops->get_sys_suspend_power_state != NULL);
Soby Mathew981487a2015-07-13 14:10:57 +0100147
148 /*
149 * Query the platform for the power_state required for system suspend
150 */
151 psci_plat_pm_ops->get_sys_suspend_power_state(state_info);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100152}
153
154/*******************************************************************************
Soby Mathew96168382014-12-17 14:47:57 +0000155 * This function verifies that the all the other cores in the system have been
156 * turned OFF and the current CPU is the last running CPU in the system.
157 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false)
158 * otherwise.
159 ******************************************************************************/
160unsigned int psci_is_last_on_cpu(void)
161{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100162 int cpu_idx, my_idx = (int) plat_my_core_pos();
Soby Mathew96168382014-12-17 14:47:57 +0000163
Soby Mathew981487a2015-07-13 14:10:57 +0100164 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
165 if (cpu_idx == my_idx) {
166 assert(psci_get_aff_info_state() == AFF_STATE_ON);
Soby Mathew96168382014-12-17 14:47:57 +0000167 continue;
168 }
169
Soby Mathew981487a2015-07-13 14:10:57 +0100170 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF)
Soby Mathew96168382014-12-17 14:47:57 +0000171 return 0;
172 }
173
174 return 1;
175}
176
177/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100178 * Routine to return the maximum power level to traverse to after a cpu has
179 * been physically powered up. It is expected to be called immediately after
180 * reset from assembler code.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100181 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100182static unsigned int get_power_on_target_pwrlvl(void)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100183{
Soby Mathew011ca182015-07-29 17:05:03 +0100184 unsigned int pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100185
186 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100187 * Assume that this cpu was suspended and retrieve its target power
188 * level. If it is invalid then it could only have been turned off
189 * earlier. PLAT_MAX_PWR_LVL will be the highest power level a
190 * cpu can be turned off to.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100191 */
Soby Mathew981487a2015-07-13 14:10:57 +0100192 pwrlvl = psci_get_suspend_pwrlvl();
Soby Mathew011ca182015-07-29 17:05:03 +0100193 if (pwrlvl == PSCI_INVALID_PWR_LVL)
Soby Mathew981487a2015-07-13 14:10:57 +0100194 pwrlvl = PLAT_MAX_PWR_LVL;
195 return pwrlvl;
Achin Guptaf6b9e992014-07-31 11:19:11 +0100196}
197
Soby Mathew981487a2015-07-13 14:10:57 +0100198/******************************************************************************
199 * Helper function to update the requested local power state array. This array
200 * does not store the requested state for the CPU power level. Hence an
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300201 * assertion is added to prevent us from accessing the CPU power level.
Soby Mathew981487a2015-07-13 14:10:57 +0100202 *****************************************************************************/
203static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
204 unsigned int cpu_idx,
205 plat_local_state_t req_pwr_state)
Achin Guptaf6b9e992014-07-31 11:19:11 +0100206{
Soby Mathew981487a2015-07-13 14:10:57 +0100207 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300208 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
209 (cpu_idx < PLATFORM_CORE_COUNT)) {
210 psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
211 }
Achin Guptaf6b9e992014-07-31 11:19:11 +0100212}
213
Soby Mathew981487a2015-07-13 14:10:57 +0100214/******************************************************************************
215 * This function initializes the psci_req_local_pwr_states.
216 *****************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +0100217void __init psci_init_req_local_pwr_states(void)
Achin Guptaa45e3972013-12-05 15:10:48 +0000218{
Soby Mathew981487a2015-07-13 14:10:57 +0100219 /* Initialize the requested state of all non CPU power domains as OFF */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100220 unsigned int pwrlvl;
221 int core;
222
223 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) {
224 for (core = 0; core < PLATFORM_CORE_COUNT; core++) {
225 psci_req_local_pwr_states[pwrlvl][core] =
226 PLAT_MAX_OFF_STATE;
227 }
228 }
Soby Mathew981487a2015-07-13 14:10:57 +0100229}
Achin Guptaa45e3972013-12-05 15:10:48 +0000230
Soby Mathew981487a2015-07-13 14:10:57 +0100231/******************************************************************************
232 * Helper function to return a reference to an array containing the local power
233 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the
234 * array will be the number of cpu power domains of which this power domain is
235 * an ancestor. These requested states will be used to determine a suitable
236 * target state for this power domain during psci state coordination. An
237 * assertion is added to prevent us from accessing the CPU power level.
238 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100239static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100240 int cpu_idx)
Soby Mathew981487a2015-07-13 14:10:57 +0100241{
242 assert(pwrlvl > PSCI_CPU_PWR_LVL);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100243
Deepika Bhavnani6bd46662019-08-15 00:56:46 +0300244 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
245 (cpu_idx < PLATFORM_CORE_COUNT)) {
246 return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
247 } else
248 return NULL;
Soby Mathew981487a2015-07-13 14:10:57 +0100249}
Achin Guptaa45e3972013-12-05 15:10:48 +0000250
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000251/*
252 * psci_non_cpu_pd_nodes can be placed either in normal memory or coherent
253 * memory.
254 *
255 * With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory,
256 * it's accessed by both cached and non-cached participants. To serve the common
257 * minimum, perform a cache flush before read and after write so that non-cached
258 * participants operate on latest data in main memory.
259 *
260 * When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent
261 * memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent.
262 * In both cases, no cache operations are required.
263 */
264
265/*
266 * Retrieve local state of non-CPU power domain node from a non-cached CPU,
267 * after any required cache maintenance operation.
268 */
269static plat_local_state_t get_non_cpu_pd_node_local_state(
270 unsigned int parent_idx)
271{
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500272#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000273 flush_dcache_range(
274 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
275 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
276#endif
277 return psci_non_cpu_pd_nodes[parent_idx].local_state;
278}
279
280/*
281 * Update local state of non-CPU power domain node from a cached CPU; perform
282 * any required cache maintenance operation afterwards.
283 */
284static void set_non_cpu_pd_node_local_state(unsigned int parent_idx,
285 plat_local_state_t state)
286{
287 psci_non_cpu_pd_nodes[parent_idx].local_state = state;
Andrew F. Davise6f28fa2018-08-30 12:13:57 -0500288#if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000289 flush_dcache_range(
290 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx],
291 sizeof(psci_non_cpu_pd_nodes[parent_idx]));
292#endif
293}
294
Soby Mathew981487a2015-07-13 14:10:57 +0100295/******************************************************************************
296 * Helper function to return the current local power state of each power domain
297 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This
298 * function will be called after a cpu is powered on to find the local state
299 * each power domain has emerged from.
300 *****************************************************************************/
Achin Gupta9b2bf252016-06-28 16:46:15 +0100301void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
302 psci_power_state_t *target_state)
Soby Mathew981487a2015-07-13 14:10:57 +0100303{
Soby Mathew011ca182015-07-29 17:05:03 +0100304 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100305 plat_local_state_t *pd_state = target_state->pwr_domain_state;
306
307 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state();
308 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
309
310 /* Copy the local power state from node to state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100311 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000312 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx);
Soby Mathew981487a2015-07-13 14:10:57 +0100313 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
314 }
315
316 /* Set the the higher levels to RUN */
317 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
318 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
319}
320
321/******************************************************************************
322 * Helper function to set the target local power state that each power domain
323 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will
324 * enter. This function will be called after coordination of requested power
325 * states has been done for each power level.
326 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100327static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100328 const psci_power_state_t *target_state)
329{
Soby Mathew011ca182015-07-29 17:05:03 +0100330 unsigned int parent_idx, lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100331 const plat_local_state_t *pd_state = target_state->pwr_domain_state;
332
333 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]);
Achin Guptaa45e3972013-12-05 15:10:48 +0000334
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100335 /*
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000336 * Need to flush as local_state might be accessed with Data Cache
Soby Mathew981487a2015-07-13 14:10:57 +0100337 * disabled during power on
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100338 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000339 psci_flush_cpu_data(psci_svc_cpu_data.local_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100340
341 parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node;
342
343 /* Copy the local_state from state_info */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100344 for (lvl = 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000345 set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]);
Soby Mathew981487a2015-07-13 14:10:57 +0100346 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
347 }
Achin Guptaa45e3972013-12-05 15:10:48 +0000348}
349
Soby Mathew981487a2015-07-13 14:10:57 +0100350
Achin Guptaa45e3972013-12-05 15:10:48 +0000351/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100352 * PSCI helper function to get the parent nodes corresponding to a cpu_index.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100353 ******************************************************************************/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100354void psci_get_parent_pwr_domain_nodes(int cpu_idx,
Soby Mathew011ca182015-07-29 17:05:03 +0100355 unsigned int end_lvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100356 unsigned int *node_index)
Soby Mathew981487a2015-07-13 14:10:57 +0100357{
358 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node;
Varun Wadekar66231d12017-06-07 09:57:42 -0700359 unsigned int i;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100360 unsigned int *node = node_index;
Soby Mathew981487a2015-07-13 14:10:57 +0100361
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100362 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) {
363 *node = parent_node;
364 node++;
Soby Mathew981487a2015-07-13 14:10:57 +0100365 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node;
366 }
367}
368
369/******************************************************************************
370 * This function is invoked post CPU power up and initialization. It sets the
371 * affinity info state, target power state and requested power state for the
372 * current CPU and all its ancestor power domains to RUN.
373 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100374void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl)
Soby Mathew981487a2015-07-13 14:10:57 +0100375{
Soby Mathew011ca182015-07-29 17:05:03 +0100376 unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl;
Soby Mathew981487a2015-07-13 14:10:57 +0100377 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
378
379 /* Reset the local_state to RUN for the non cpu power domains. */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100380 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000381 set_non_cpu_pd_node_local_state(parent_idx,
382 PSCI_LOCAL_STATE_RUN);
Soby Mathew981487a2015-07-13 14:10:57 +0100383 psci_set_req_local_pwr_state(lvl,
384 cpu_idx,
385 PSCI_LOCAL_STATE_RUN);
386 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
387 }
388
389 /* Set the affinity info state to ON */
390 psci_set_aff_info_state(AFF_STATE_ON);
391
392 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000393 psci_flush_cpu_data(psci_svc_cpu_data);
Soby Mathew981487a2015-07-13 14:10:57 +0100394}
395
396/******************************************************************************
397 * This function is passed the local power states requested for each power
398 * domain (state_info) between the current CPU domain and its ancestors until
399 * the target power level (end_pwrlvl). It updates the array of requested power
400 * states with this information.
401 *
402 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
403 * retrieves the states requested by all the cpus of which the power domain at
404 * that level is an ancestor. It passes this information to the platform to
405 * coordinate and return the target power state. If the target state for a level
406 * is RUN then subsequent levels are not considered. At the CPU level, state
407 * coordination is not required. Hence, the requested and the target states are
408 * the same.
409 *
410 * The 'state_info' is updated with the target state for each level between the
411 * CPU and the 'end_pwrlvl' and returned to the caller.
412 *
413 * This function will only be invoked with data cache enabled and while
414 * powering down a core.
415 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100416void psci_do_state_coordination(unsigned int end_pwrlvl,
417 psci_power_state_t *state_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100418{
Soby Mathew981487a2015-07-13 14:10:57 +0100419 unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100420 int start_idx;
421 unsigned int ncpus;
Soby Mathew981487a2015-07-13 14:10:57 +0100422 plat_local_state_t target_state, *req_states;
423
Soby Mathew1298e692016-02-02 14:23:10 +0000424 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
Soby Mathew981487a2015-07-13 14:10:57 +0100425 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
426
427 /* For level 0, the requested state will be equivalent
428 to target state */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100429 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100430
431 /* First update the requested power state */
432 psci_set_req_local_pwr_state(lvl, cpu_idx,
433 state_info->pwr_domain_state[lvl]);
434
435 /* Get the requested power states for this power level */
436 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
437 req_states = psci_get_req_local_pwr_states(lvl, start_idx);
438
439 /*
440 * Let the platform coordinate amongst the requested states at
441 * this power level and return the target local power state.
442 */
443 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus;
444 target_state = plat_get_target_pwr_state(lvl,
445 req_states,
446 ncpus);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100447
Soby Mathew981487a2015-07-13 14:10:57 +0100448 state_info->pwr_domain_state[lvl] = target_state;
449
450 /* Break early if the negotiated target power state is RUN */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100451 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0)
Soby Mathew981487a2015-07-13 14:10:57 +0100452 break;
453
454 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
455 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100456
457 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100458 * This is for cases when we break out of the above loop early because
459 * the target power state is RUN at a power level < end_pwlvl.
460 * We update the requested power state from state_info and then
461 * set the target state as RUN.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100462 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100463 for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100464 psci_set_req_local_pwr_state(lvl, cpu_idx,
465 state_info->pwr_domain_state[lvl]);
466 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100467
Soby Mathew981487a2015-07-13 14:10:57 +0100468 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100469
Soby Mathew981487a2015-07-13 14:10:57 +0100470 /* Update the target state in the power domain nodes */
471 psci_set_target_local_pwr_states(end_pwrlvl, state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100472}
473
Soby Mathew981487a2015-07-13 14:10:57 +0100474/******************************************************************************
475 * This function validates a suspend request by making sure that if a standby
476 * state is requested then no power level is turned off and the highest power
477 * level is placed in a standby/retention state.
478 *
479 * It also ensures that the state level X will enter is not shallower than the
480 * state level X + 1 will enter.
481 *
482 * This validation will be enabled only for DEBUG builds as the platform is
483 * expected to perform these validations as well.
484 *****************************************************************************/
485int psci_validate_suspend_req(const psci_power_state_t *state_info,
486 unsigned int is_power_down_state)
Achin Gupta0959db52013-12-02 17:33:04 +0000487{
Soby Mathew981487a2015-07-13 14:10:57 +0100488 unsigned int max_off_lvl, target_lvl, max_retn_lvl;
489 plat_local_state_t state;
490 plat_local_state_type_t req_state_type, deepest_state_type;
491 int i;
Achin Gupta0959db52013-12-02 17:33:04 +0000492
Soby Mathew981487a2015-07-13 14:10:57 +0100493 /* Find the target suspend power level */
494 target_lvl = psci_find_target_suspend_lvl(state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100495 if (target_lvl == PSCI_INVALID_PWR_LVL)
Achin Gupta0959db52013-12-02 17:33:04 +0000496 return PSCI_E_INVALID_PARAMS;
497
Soby Mathew981487a2015-07-13 14:10:57 +0100498 /* All power domain levels are in a RUN state to begin with */
499 deepest_state_type = STATE_TYPE_RUN;
500
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100501 for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) {
Soby Mathew981487a2015-07-13 14:10:57 +0100502 state = state_info->pwr_domain_state[i];
503 req_state_type = find_local_state_type(state);
504
505 /*
506 * While traversing from the highest power level to the lowest,
507 * the state requested for lower levels has to be the same or
508 * deeper i.e. equal to or greater than the state at the higher
509 * levels. If this condition is true, then the requested state
510 * becomes the deepest state encountered so far.
511 */
512 if (req_state_type < deepest_state_type)
513 return PSCI_E_INVALID_PARAMS;
514 deepest_state_type = req_state_type;
515 }
516
517 /* Find the highest off power level */
518 max_off_lvl = psci_find_max_off_lvl(state_info);
519
520 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */
Soby Mathew011ca182015-07-29 17:05:03 +0100521 max_retn_lvl = PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100522 if (target_lvl != max_off_lvl)
523 max_retn_lvl = target_lvl;
524
525 /*
526 * If this is not a request for a power down state then max off level
527 * has to be invalid and max retention level has to be a valid power
528 * level.
529 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100530 if ((is_power_down_state == 0U) &&
531 ((max_off_lvl != PSCI_INVALID_PWR_LVL) ||
532 (max_retn_lvl == PSCI_INVALID_PWR_LVL)))
Achin Gupta0959db52013-12-02 17:33:04 +0000533 return PSCI_E_INVALID_PARAMS;
534
535 return PSCI_E_SUCCESS;
536}
537
Soby Mathew981487a2015-07-13 14:10:57 +0100538/******************************************************************************
539 * This function finds the highest power level which will be powered down
540 * amongst all the power levels specified in the 'state_info' structure
541 *****************************************************************************/
542unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info)
Achin Guptacab78e42014-07-28 00:09:01 +0100543{
Soby Mathew981487a2015-07-13 14:10:57 +0100544 int i;
Achin Guptacab78e42014-07-28 00:09:01 +0100545
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100546 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
547 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0)
548 return (unsigned int) i;
Soby Mathew981487a2015-07-13 14:10:57 +0100549 }
550
Soby Mathew011ca182015-07-29 17:05:03 +0100551 return PSCI_INVALID_PWR_LVL;
Soby Mathew981487a2015-07-13 14:10:57 +0100552}
553
554/******************************************************************************
555 * This functions finds the level of the highest power domain which will be
556 * placed in a low power state during a suspend operation.
557 *****************************************************************************/
558unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info)
559{
560 int i;
561
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100562 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) {
563 if (is_local_state_run(state_info->pwr_domain_state[i]) == 0)
564 return (unsigned int) i;
Achin Guptacab78e42014-07-28 00:09:01 +0100565 }
Soby Mathew981487a2015-07-13 14:10:57 +0100566
Soby Mathew011ca182015-07-29 17:05:03 +0100567 return PSCI_INVALID_PWR_LVL;
Achin Guptacab78e42014-07-28 00:09:01 +0100568}
569
570/*******************************************************************************
Andrew F. Davis74e89782019-06-04 10:46:54 -0400571 * This function is passed the highest level in the topology tree that the
572 * operation should be applied to and a list of node indexes. It picks up locks
573 * from the node index list in order of increasing power domain level in the
574 * range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000575 ******************************************************************************/
Andrew F. Davis74e89782019-06-04 10:46:54 -0400576void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
577 const unsigned int *parent_nodes)
Achin Gupta0959db52013-12-02 17:33:04 +0000578{
Andrew F. Davis74e89782019-06-04 10:46:54 -0400579 unsigned int parent_idx;
Soby Mathew011ca182015-07-29 17:05:03 +0100580 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000581
Soby Mathew981487a2015-07-13 14:10:57 +0100582 /* No locking required for level 0. Hence start locking from level 1 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100583 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) {
Andrew F. Davis74e89782019-06-04 10:46:54 -0400584 parent_idx = parent_nodes[level - 1U];
Soby Mathew981487a2015-07-13 14:10:57 +0100585 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000586 }
587}
588
589/*******************************************************************************
Andrew F. Davis74e89782019-06-04 10:46:54 -0400590 * This function is passed the highest level in the topology tree that the
591 * operation should be applied to and a list of node indexes. It releases the
592 * locks in order of decreasing power domain level in the range specified.
Achin Gupta0959db52013-12-02 17:33:04 +0000593 ******************************************************************************/
Andrew F. Davis74e89782019-06-04 10:46:54 -0400594void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
595 const unsigned int *parent_nodes)
Achin Gupta0959db52013-12-02 17:33:04 +0000596{
Andrew F. Davis74e89782019-06-04 10:46:54 -0400597 unsigned int parent_idx;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100598 unsigned int level;
Achin Gupta0959db52013-12-02 17:33:04 +0000599
Soby Mathew981487a2015-07-13 14:10:57 +0100600 /* Unlock top down. No unlocking required for level 0. */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100601 for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1U; level--) {
602 parent_idx = parent_nodes[level - 1U];
Soby Mathew981487a2015-07-13 14:10:57 +0100603 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]);
Achin Gupta0959db52013-12-02 17:33:04 +0000604 }
605}
606
607/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100608 * Simple routine to determine whether a mpidr is valid or not.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100609 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100610int psci_validate_mpidr(u_register_t mpidr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100611{
Soby Mathew981487a2015-07-13 14:10:57 +0100612 if (plat_core_pos_by_mpidr(mpidr) < 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100613 return PSCI_E_INVALID_PARAMS;
Soby Mathew981487a2015-07-13 14:10:57 +0100614
615 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100616}
617
618/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100619 * This function determines the full entrypoint information for the requested
Soby Mathew8595b872015-01-06 15:36:38 +0000620 * PSCI entrypoint on power on/resume and returns it.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100621 ******************************************************************************/
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700622#ifdef __aarch64__
Soby Mathewf1f97a12015-07-15 12:13:26 +0100623static int psci_get_ns_ep_info(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100624 uintptr_t entrypoint,
625 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100626{
Soby Mathewa0fedc42016-06-16 14:52:04 +0100627 u_register_t ep_attr, sctlr;
Soby Mathew011ca182015-07-29 17:05:03 +0100628 unsigned int daif, ee, mode;
Soby Mathewa0fedc42016-06-16 14:52:04 +0100629 u_register_t ns_scr_el3 = read_scr_el3();
630 u_register_t ns_sctlr_el1 = read_sctlr_el1();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100631
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100632 sctlr = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
633 read_sctlr_el2() : ns_sctlr_el1;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100634 ee = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100635
Andrew Thoelke4e126072014-06-04 21:10:52 +0100636 ep_attr = NON_SECURE | EP_ST_DISABLE;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100637 if ((sctlr & SCTLR_EE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100638 ep_attr |= EP_EE_BIG;
639 ee = 1;
640 }
Soby Mathew8595b872015-01-06 15:36:38 +0000641 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100642
Soby Mathew8595b872015-01-06 15:36:38 +0000643 ep->pc = entrypoint;
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000644 zeromem(&ep->args, sizeof(ep->args));
Soby Mathew8595b872015-01-06 15:36:38 +0000645 ep->args.arg0 = context_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100646
647 /*
648 * Figure out whether the cpu enters the non-secure address space
649 * in aarch32 or aarch64
650 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100651 if ((ns_scr_el3 & SCR_RW_BIT) != 0U) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100652
653 /*
654 * Check whether a Thumb entry point has been provided for an
655 * aarch64 EL
656 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100657 if ((entrypoint & 0x1UL) != 0UL)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100658 return PSCI_E_INVALID_ADDRESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100659
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100660 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100661
Soby Mathew8595b872015-01-06 15:36:38 +0000662 ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100663 } else {
664
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100665 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
666 MODE32_hyp : MODE32_svc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100667
668 /*
669 * TODO: Choose async. exception bits if HYP mode is not
670 * implemented according to the values of SCR.{AW, FW} bits
671 */
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100672 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
673
Soby Mathew8595b872015-01-06 15:36:38 +0000674 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100675 }
676
Andrew Thoelke4e126072014-06-04 21:10:52 +0100677 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100678}
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700679#else /* !__aarch64__ */
680static int psci_get_ns_ep_info(entry_point_info_t *ep,
681 uintptr_t entrypoint,
682 u_register_t context_id)
683{
684 u_register_t ep_attr;
685 unsigned int aif, ee, mode;
686 u_register_t scr = read_scr();
687 u_register_t ns_sctlr, sctlr;
688
689 /* Switch to non secure state */
690 write_scr(scr | SCR_NS_BIT);
691 isb();
692 ns_sctlr = read_sctlr();
693
694 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr;
695
696 /* Return to original state */
697 write_scr(scr);
698 isb();
699 ee = 0;
700
701 ep_attr = NON_SECURE | EP_ST_DISABLE;
702 if (sctlr & SCTLR_EE_BIT) {
703 ep_attr |= EP_EE_BIG;
704 ee = 1;
705 }
706 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr);
707
708 ep->pc = entrypoint;
709 zeromem(&ep->args, sizeof(ep->args));
710 ep->args.arg0 = context_id;
711
712 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc;
713
714 /*
715 * TODO: Choose async. exception bits if HYP mode is not
716 * implemented according to the values of SCR.{AW, FW} bits
717 */
718 aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT;
719
720 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif);
721
722 return PSCI_E_SUCCESS;
723}
724
725#endif /* __aarch64__ */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100726
727/*******************************************************************************
Soby Mathewf1f97a12015-07-15 12:13:26 +0100728 * This function validates the entrypoint with the platform layer if the
729 * appropriate pm_ops hook is exported by the platform and returns the
730 * 'entry_point_info'.
731 ******************************************************************************/
732int psci_validate_entry_point(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100733 uintptr_t entrypoint,
734 u_register_t context_id)
Soby Mathewf1f97a12015-07-15 12:13:26 +0100735{
736 int rc;
737
738 /* Validate the entrypoint using platform psci_ops */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100739 if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100740 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint);
741 if (rc != PSCI_E_SUCCESS)
742 return PSCI_E_INVALID_ADDRESS;
743 }
744
745 /*
746 * Verify and derive the re-entry information for
747 * the non-secure world from the non-secure state from
748 * where this call originated.
749 */
750 rc = psci_get_ns_ep_info(ep, entrypoint, context_id);
751 return rc;
752}
753
754/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100755 * Generic handler which is called when a cpu is physically powered on. It
Soby Mathew981487a2015-07-13 14:10:57 +0100756 * traverses the node information and finds the highest power level powered
757 * off and performs generic, architectural, platform setup and state management
758 * to power on that power level and power levels below it.
759 * e.g. For a cpu that's been powered on, it will call the platform specific
760 * code to enable the gic cpu interface and for a cluster it will enable
761 * coherency at the interconnect level in addition to gic cpu interface.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100762 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100763void psci_warmboot_entrypoint(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100764{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100765 unsigned int end_pwrlvl;
766 int cpu_idx = (int) plat_my_core_pos();
Andrew F. Davis74e89782019-06-04 10:46:54 -0400767 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
Soby Mathew981487a2015-07-13 14:10:57 +0100768 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100769
Achin Gupta4f6ad662013-10-25 09:08:21 +0100770 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100771 * Verify that we have been explicitly turned ON or resumed from
772 * suspend.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100773 */
Soby Mathew981487a2015-07-13 14:10:57 +0100774 if (psci_get_aff_info_state() == AFF_STATE_OFF) {
775 ERROR("Unexpected affinity info state");
James Morrissey40a6f642014-02-10 14:24:36 +0000776 panic();
Soby Mathew981487a2015-07-13 14:10:57 +0100777 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100778
779 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100780 * Get the maximum power domain level to traverse to after this cpu
781 * has been physically powered up.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100782 */
Soby Mathew981487a2015-07-13 14:10:57 +0100783 end_pwrlvl = get_power_on_target_pwrlvl();
Achin Guptaf6b9e992014-07-31 11:19:11 +0100784
Andrew F. Davis74e89782019-06-04 10:46:54 -0400785 /* Get the parent nodes */
786 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes);
787
Achin Guptaf6b9e992014-07-31 11:19:11 +0100788 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100789 * This function acquires the lock corresponding to each power level so
790 * that by the time all locks are taken, the system topology is snapshot
791 * and state management can be done safely.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100792 */
Andrew F. Davis74e89782019-06-04 10:46:54 -0400793 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100794
Soby Mathew8336f682017-10-16 15:19:31 +0100795 psci_get_target_local_pwr_states(end_pwrlvl, &state_info);
796
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100797#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000798 plat_psci_stat_accounting_stop(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100799#endif
800
Achin Gupta4f6ad662013-10-25 09:08:21 +0100801 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100802 * This CPU could be resuming from suspend or it could have just been
803 * turned on. To distinguish between these 2 cases, we examine the
804 * affinity state of the CPU:
805 * - If the affinity state is ON_PENDING then it has just been
806 * turned on.
807 * - Else it is resuming from suspend.
808 *
809 * Depending on the type of warm reset identified, choose the right set
810 * of power management handler and perform the generic, architecture
811 * and platform specific handling.
Achin Guptacab78e42014-07-28 00:09:01 +0100812 */
Soby Mathew981487a2015-07-13 14:10:57 +0100813 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING)
814 psci_cpu_on_finish(cpu_idx, &state_info);
815 else
816 psci_cpu_suspend_finish(cpu_idx, &state_info);
Achin Guptacab78e42014-07-28 00:09:01 +0100817
818 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100819 * Set the requested and target state of this CPU and all the higher
820 * power domains which are ancestors of this CPU to run.
Achin Guptaf6b9e992014-07-31 11:19:11 +0100821 */
Soby Mathew981487a2015-07-13 14:10:57 +0100822 psci_set_pwr_domains_to_run(end_pwrlvl);
Achin Guptaf6b9e992014-07-31 11:19:11 +0100823
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100824#if ENABLE_PSCI_STAT
825 /*
826 * Update PSCI stats.
827 * Caches are off when writing stats data on the power down path.
828 * Since caches are now enabled, it's necessary to do cache
829 * maintenance before reading that same data.
830 */
dp-arm66abfbe2017-01-31 13:01:04 +0000831 psci_stats_update_pwr_up(end_pwrlvl, &state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100832#endif
833
Achin Guptaf6b9e992014-07-31 11:19:11 +0100834 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100835 * This loop releases the lock corresponding to each power level
Achin Gupta0959db52013-12-02 17:33:04 +0000836 * in the reverse order to which they were acquired.
837 */
Andrew F. Davis74e89782019-06-04 10:46:54 -0400838 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100839}
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000840
841/*******************************************************************************
842 * This function initializes the set of hooks that PSCI invokes as part of power
843 * management operation. The power management hooks are expected to be provided
844 * by the SPD, after it finishes all its initialization
845 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100846void psci_register_spd_pm_hook(const spd_pm_ops_t *pm)
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000847{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100848 assert(pm != NULL);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000849 psci_spd_pm = pm;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000850
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100851 if (pm->svc_migrate != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000852 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64);
853
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100854 if (pm->svc_migrate_info != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000855 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64)
856 | define_psci_cap(PSCI_MIG_INFO_TYPE);
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000857}
Juan Castillo4dc4a472014-08-12 11:17:06 +0100858
859/*******************************************************************************
Soby Mathew110fe362014-10-23 10:35:34 +0100860 * This function invokes the migrate info hook in the spd_pm_ops. It performs
861 * the necessary return value validation. If the Secure Payload is UP and
862 * migrate capable, it returns the mpidr of the CPU on which the Secure payload
863 * is resident through the mpidr parameter. Else the value of the parameter on
864 * return is undefined.
865 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +0100866int psci_spd_migrate_info(u_register_t *mpidr)
Soby Mathew110fe362014-10-23 10:35:34 +0100867{
868 int rc;
869
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100870 if ((psci_spd_pm == NULL) || (psci_spd_pm->svc_migrate_info == NULL))
Soby Mathew110fe362014-10-23 10:35:34 +0100871 return PSCI_E_NOT_SUPPORTED;
872
873 rc = psci_spd_pm->svc_migrate_info(mpidr);
874
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100875 assert((rc == PSCI_TOS_UP_MIG_CAP) || (rc == PSCI_TOS_NOT_UP_MIG_CAP) ||
876 (rc == PSCI_TOS_NOT_PRESENT_MP) || (rc == PSCI_E_NOT_SUPPORTED));
Soby Mathew110fe362014-10-23 10:35:34 +0100877
878 return rc;
879}
880
881
882/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100883 * This function prints the state of all power domains present in the
Juan Castillo4dc4a472014-08-12 11:17:06 +0100884 * system
885 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100886void psci_print_power_domain_map(void)
Juan Castillo4dc4a472014-08-12 11:17:06 +0100887{
888#if LOG_LEVEL >= LOG_LEVEL_INFO
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100889 int idx;
Soby Mathew981487a2015-07-13 14:10:57 +0100890 plat_local_state_t state;
891 plat_local_state_type_t state_type;
892
Juan Castillo4dc4a472014-08-12 11:17:06 +0100893 /* This array maps to the PSCI_STATE_X definitions in psci.h */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100894 static const char * const psci_state_type_str[] = {
Juan Castillo4dc4a472014-08-12 11:17:06 +0100895 "ON",
Soby Mathew981487a2015-07-13 14:10:57 +0100896 "RETENTION",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100897 "OFF",
Juan Castillo4dc4a472014-08-12 11:17:06 +0100898 };
899
Soby Mathew981487a2015-07-13 14:10:57 +0100900 INFO("PSCI Power Domain Map:\n");
901 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT);
902 idx++) {
903 state_type = find_local_state_type(
904 psci_non_cpu_pd_nodes[idx].local_state);
905 INFO(" Domain Node : Level %u, parent_node %d,"
906 " State %s (0x%x)\n",
907 psci_non_cpu_pd_nodes[idx].level,
908 psci_non_cpu_pd_nodes[idx].parent_node,
909 psci_state_type_str[state_type],
910 psci_non_cpu_pd_nodes[idx].local_state);
911 }
912
913 for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) {
914 state = psci_get_cpu_local_state_by_idx(idx);
915 state_type = find_local_state_type(state);
Soby Mathewa0fedc42016-06-16 14:52:04 +0100916 INFO(" CPU Node : MPID 0x%llx, parent_node %d,"
Soby Mathew981487a2015-07-13 14:10:57 +0100917 " State %s (0x%x)\n",
Soby Mathewa0fedc42016-06-16 14:52:04 +0100918 (unsigned long long)psci_cpu_pd_nodes[idx].mpidr,
Soby Mathew981487a2015-07-13 14:10:57 +0100919 psci_cpu_pd_nodes[idx].parent_node,
920 psci_state_type_str[state_type],
921 psci_get_cpu_local_state_by_idx(idx));
Juan Castillo4dc4a472014-08-12 11:17:06 +0100922 }
923#endif
924}
Soby Mathew981487a2015-07-13 14:10:57 +0100925
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000926/******************************************************************************
927 * Return whether any secondaries were powered up with CPU_ON call. A CPU that
928 * have ever been powered up would have set its MPDIR value to something other
929 * than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to
930 * PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is
931 * meaningful only when called on the primary CPU during early boot.
932 *****************************************************************************/
933int psci_secondaries_brought_up(void)
934{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100935 unsigned int idx, n_valid = 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000936
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100937 for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) {
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000938 if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR)
939 n_valid++;
940 }
941
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100942 assert(n_valid > 0U);
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000943
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100944 return (n_valid > 1U) ? 1 : 0;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000945}
946
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000947/*******************************************************************************
948 * Initiate power down sequence, by calling power down operations registered for
949 * this CPU.
950 ******************************************************************************/
951void psci_do_pwrdown_sequence(unsigned int power_level)
952{
953#if HW_ASSISTED_COHERENCY
954 /*
955 * With hardware-assisted coherency, the CPU drivers only initiate the
956 * power down sequence, without performing cache-maintenance operations
Andrew F. Davis564f9542018-08-30 12:08:01 -0500957 * in software. Data caches enabled both before and after this call.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000958 */
959 prepare_cpu_pwr_dwn(power_level);
960#else
961 /*
962 * Without hardware-assisted coherency, the CPU drivers disable data
Andrew F. Davis564f9542018-08-30 12:08:01 -0500963 * caches, then perform cache-maintenance operations in software.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000964 *
Andrew F. Davis564f9542018-08-30 12:08:01 -0500965 * This also calls prepare_cpu_pwr_dwn() to initiate power down
966 * sequence, but that function will return with data caches disabled.
967 * We must ensure that the stack memory is flushed out to memory before
968 * we start popping from it again.
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000969 */
970 psci_do_pwrdown_cache_maintenance(power_level);
971#endif
972}