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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +00008#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <drivers/arm/gicv2.h>
10#include <drivers/arm/gicv3.h>
Dan Handley4fd2f5c2014-08-04 11:41:20 +010011#include <platform_def.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000012#include <v2m_def.h>
Vikram Kanigiri96377452014-04-24 11:02:16 +010013#include "../drivers/pwrc/fvp_pwrc.h"
Dan Handley2b6b5742015-03-19 19:17:53 +000014#include "../fvp_def.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010015
Vikram Kanigiri96377452014-04-24 11:02:16 +010016 .globl plat_secondary_cold_boot_setup
Soby Mathewfec4eb72015-07-01 16:16:20 +010017 .globl plat_get_my_entrypoint
Soby Mathewfec4eb72015-07-01 16:16:20 +010018 .globl plat_is_my_cpu_primary
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000019 .globl plat_arm_calc_core_pos
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Dan Handleyea451572014-05-15 14:53:30 +010021 .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
Soby Mathewef81bc52018-10-12 17:08:28 +010022 mov_imm \x_tmp, V2M_SYSREGS_BASE + V2M_SYS_ID
Vikram Kanigiri96377452014-04-24 11:02:16 +010023 ldr \w_tmp, [\x_tmp]
Dan Handley2b6b5742015-03-19 19:17:53 +000024 ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
Vikram Kanigiri96377452014-04-24 11:02:16 +010025 cmp \w_tmp, #BLD_GIC_VE_MMAP
26 csel \res, \param1, \param2, eq
27 .endm
28
29 /* -----------------------------------------------------
30 * void plat_secondary_cold_boot_setup (void);
31 *
32 * This function performs any platform specific actions
33 * needed for a secondary cpu after a cold reset e.g
34 * mark the cpu's presence, mechanism to place it in a
35 * holding pen etc.
36 * TODO: Should we read the PSYS register to make sure
37 * that the request has gone through.
38 * -----------------------------------------------------
39 */
40func plat_secondary_cold_boot_setup
Sandrine Bailleuxd47c9a52015-10-02 14:35:25 +010041#ifndef EL3_PAYLOAD_BASE
Vikram Kanigiri96377452014-04-24 11:02:16 +010042 /* ---------------------------------------------
43 * Power down this cpu.
44 * TODO: Do we need to worry about powering the
45 * cluster down as well here. That will need
46 * locks which we won't have unless an elf-
47 * loader zeroes out the zi section.
48 * ---------------------------------------------
49 */
50 mrs x0, mpidr_el1
Soby Mathewef81bc52018-10-12 17:08:28 +010051 mov_imm x1, PWRC_BASE
Vikram Kanigiri96377452014-04-24 11:02:16 +010052 str w0, [x1, #PPOFFR_OFF]
53
54 /* ---------------------------------------------
Soby Mathew12012dd2015-10-26 14:01:53 +000055 * Disable GIC bypass as well
Vikram Kanigiri96377452014-04-24 11:02:16 +010056 * ---------------------------------------------
57 */
Soby Mathew12012dd2015-10-26 14:01:53 +000058 /* Check for GICv3 system register access */
59 mrs x0, id_aa64pfr0_el1
60 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
61 cmp x0, #1
62 b.ne gicv2_bypass_disable
63
64 /* Check for SRE enable */
65 mrs x1, ICC_SRE_EL3
66 tst x1, #ICC_SRE_SRE_BIT
67 b.eq gicv2_bypass_disable
68
69 mrs x2, ICC_SRE_EL3
70 orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
71 msr ICC_SRE_EL3, x2
72 b secondary_cold_boot_wait
73
74gicv2_bypass_disable:
Soby Mathewef81bc52018-10-12 17:08:28 +010075 mov_imm x0, VE_GICC_BASE
76 mov_imm x1, BASE_GICC_BASE
Dan Handleyea451572014-05-15 14:53:30 +010077 fvp_choose_gicmmap x0, x1, x2, w2, x1
Vikram Kanigiri96377452014-04-24 11:02:16 +010078 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
79 orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
80 str w0, [x1, #GICC_CTLR]
81
Soby Mathew12012dd2015-10-26 14:01:53 +000082secondary_cold_boot_wait:
Vikram Kanigiri96377452014-04-24 11:02:16 +010083 /* ---------------------------------------------
84 * There is no sane reason to come out of this
85 * wfi so panic if we do. This cpu will be pow-
86 * ered on and reset by the cpu_on pm api
87 * ---------------------------------------------
88 */
89 dsb sy
90 wfi
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000091 no_ret plat_panic_handler
Sandrine Bailleuxd47c9a52015-10-02 14:35:25 +010092#else
93 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
94
95 /* Wait until the entrypoint gets populated */
96poll_mailbox:
97 ldr x1, [x0]
98 cbz x1, 1f
99 br x1
1001:
101 wfe
102 b poll_mailbox
103#endif /* EL3_PAYLOAD_BASE */
Kévin Petita877c252015-03-24 14:03:57 +0000104endfunc plat_secondary_cold_boot_setup
Vikram Kanigiri96377452014-04-24 11:02:16 +0100105
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100106 /* ---------------------------------------------------------------------
Soby Mathewa0fedc42016-06-16 14:52:04 +0100107 * uintptr_t plat_get_my_entrypoint (void);
Vikram Kanigiri96377452014-04-24 11:02:16 +0100108 *
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100109 * Main job of this routine is to distinguish between a cold and warm
110 * boot. On FVP, this information can be queried from the power
111 * controller. The Power Control SYS Status Register (PSYSR) indicates
112 * the wake-up reason for the CPU.
113 *
114 * For a cold boot, return 0.
115 * For a warm boot, read the mailbox and return the address it contains.
Vikram Kanigiri96377452014-04-24 11:02:16 +0100116 *
Vikram Kanigiri96377452014-04-24 11:02:16 +0100117 * TODO: PSYSR is a common register and should be
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000118 * accessed using locks. Since it is not possible
Vikram Kanigiri96377452014-04-24 11:02:16 +0100119 * to use locks immediately after a cold reset
120 * we are relying on the fact that after a cold
121 * reset all cpus will read the same WK field
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100122 * ---------------------------------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +0100123 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100124func plat_get_my_entrypoint
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100125 /* ---------------------------------------------------------------------
126 * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
127 * WakeRequest signal" then it is a warm boot.
128 * ---------------------------------------------------------------------
129 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100130 mrs x2, mpidr_el1
Soby Mathewef81bc52018-10-12 17:08:28 +0100131 mov_imm x1, PWRC_BASE
Vikram Kanigiri96377452014-04-24 11:02:16 +0100132 str w2, [x1, #PSYSR_OFF]
133 ldr w2, [x1, #PSYSR_OFF]
Soby Mathew2ae23192015-04-30 12:27:41 +0100134 ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
Juan Castillo9a5b56e2014-07-11 10:23:18 +0100135 cmp w2, #WKUP_PPONR
136 beq warm_reset
137 cmp w2, #WKUP_GICREQ
138 beq warm_reset
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100139
140 /* Cold reset */
Juan Castillo9a5b56e2014-07-11 10:23:18 +0100141 mov x0, #0
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100142 ret
143
Vikram Kanigiri96377452014-04-24 11:02:16 +0100144warm_reset:
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100145 /* ---------------------------------------------------------------------
146 * A mailbox is maintained in the trusted SRAM. It is flushed out of the
147 * caches after every update using normal memory so it is safe to read
148 * it here with SO attributes.
149 * ---------------------------------------------------------------------
Vikram Kanigiri96377452014-04-24 11:02:16 +0100150 */
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100151 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100152 ldr x0, [x0]
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000153 cbz x0, _panic_handler
Sandrine Bailleuxdaf9a9d2015-07-10 16:49:31 +0100154 ret
155
156 /* ---------------------------------------------------------------------
157 * The power controller indicates this is a warm reset but the mailbox
158 * is empty. This should never happen!
159 * ---------------------------------------------------------------------
160 */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000161_panic_handler:
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000162 no_ret plat_panic_handler
Soby Mathewfec4eb72015-07-01 16:16:20 +0100163endfunc plat_get_my_entrypoint
Vikram Kanigiri96377452014-04-24 11:02:16 +0100164
Soby Matheweb3bbf12015-06-08 12:32:50 +0100165 /* -----------------------------------------------------
166 * unsigned int plat_is_my_cpu_primary (void);
167 *
168 * Find out whether the current cpu is the primary
169 * cpu.
170 * -----------------------------------------------------
171 */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100172func plat_is_my_cpu_primary
173 mrs x0, mpidr_el1
Soby Mathewef81bc52018-10-12 17:08:28 +0100174 mov_imm x1, MPIDR_AFFINITY_MASK
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000175 and x0, x0, x1
Juan Castillob3dbeb02014-07-16 15:53:43 +0100176 cmp x0, #FVP_PRIMARY_CPU
Soby Matheweb3bbf12015-06-08 12:32:50 +0100177 cset w0, eq
Juan Castillob3dbeb02014-07-16 15:53:43 +0100178 ret
Soby Mathewfec4eb72015-07-01 16:16:20 +0100179endfunc plat_is_my_cpu_primary
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000180
Wang Feng8d22ec32018-03-15 15:32:41 +0800181 /* ---------------------------------------------------------------------
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000182 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
183 *
184 * Function to calculate the core position on FVP.
185 *
Wang Feng8d22ec32018-03-15 15:32:41 +0800186 * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) +
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000187 * (CPUId * FVP_MAX_PE_PER_CPU) +
188 * ThreadId
Wang Feng8d22ec32018-03-15 15:32:41 +0800189 *
190 * which can be simplified as:
191 *
192 * ((ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU)
193 * + ThreadId
194 * ---------------------------------------------------------------------
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000195 */
196func plat_arm_calc_core_pos
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000197 /*
198 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
199 * look as if in a multi-threaded implementation.
200 */
201 tst x0, #MPIDR_MT_MASK
202 lsl x3, x0, #MPIDR_AFFINITY_BITS
203 csel x3, x3, x0, eq
204
205 /* Extract individual affinity fields from MPIDR */
206 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
207 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
208 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
209
210 /* Compute linear position */
Wang Feng8d22ec32018-03-15 15:32:41 +0800211 mov x4, #FVP_MAX_CPUS_PER_CLUSTER
212 madd x1, x2, x4, x1
213 mov x5, #FVP_MAX_PE_PER_CPU
214 madd x0, x1, x5, x0
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000215 ret
216endfunc plat_arm_calc_core_pos