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Dan Handley610e7e12018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002=============================
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5.. section-numbering::
6 :suffix: .
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8.. contents::
9
10This document describes the various build options present in the CPU specific
11operations framework to enable errata workarounds and to enable optimizations
12for a specific CPU on a platform.
13
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000014Security Vulnerability Workarounds
15----------------------------------
16
Dan Handley610e7e12018-03-01 18:44:00 +000017TF-A exports a series of build flags which control which security
18vulnerability workarounds should be applied at runtime.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000019
20- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010021 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
22 of the PEs in the system need the workaround. Setting this flag to 0 provides
23 no performance benefit for non-affected platforms, it just helps to comply
24 with the recommendation in the spec regarding workaround discovery.
25 Defaults to 1.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000026
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010027- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
28 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
29 the default value of 1 even on platforms that are unaffected by
30 CVE-2018-3639, in order to comply with the recommendation in the spec
31 regarding workaround discovery.
32
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010033- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
34 `CVE-2018-3639`_. This build option should be set to 1 if the target
35 platform contains at least 1 CPU that requires dynamic mitigation.
36 Defaults to 0.
37
Douglas Raillardd7c21b72017-06-28 15:23:03 +010038CPU Errata Workarounds
39----------------------
40
Dan Handley610e7e12018-03-01 18:44:00 +000041TF-A exports a series of build flags which control the errata workarounds that
42are applied to each CPU by the reset handler. The errata details can be found
43in the CPU specific errata documents published by Arm:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044
45- `Cortex-A53 MPCore Software Developers Errata Notice`_
46- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +010047- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048
49The errata workarounds are implemented for a particular revision or a set of
50processor revisions. This is checked by the reset handler at runtime. Each
51errata workaround is identified by its ``ID`` as specified in the processor's
52errata notice document. The format of the define used to enable/disable the
53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
54is for example ``A57`` for the ``Cortex_A57`` CPU.
55
56Refer to the section *CPU errata status reporting* in
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +010057`Firmware Design guide`_ for information on how to write errata workaround
58functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059
60All workarounds are disabled by default. The platform is responsible for
61enabling these workarounds according to its requirement by defining the
62errata workaround build flags in the platform specific makefile. In case
63these workarounds are enabled for the wrong CPU revision then the errata
64workaround is not applied. In the DEBUG build, this is indicated by
65printing a warning to the crash console.
66
67In the current implementation, a platform which has more than 1 variant
68with different revisions of a processor has no runtime mechanism available
69for it to specify which errata workarounds should be enabled or not.
70
John Tsichritzis4daa1de2018-07-23 09:11:59 +010071The value of the build flags is 0 by default, that is, disabled. A value of 1
72will enable it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
John Tsichritzis4daa1de2018-07-23 09:11:59 +010074For Cortex-A53, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +010075
76- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
77 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
78
Douglas Raillardb52353a2017-07-17 14:14:52 +010079- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
80 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
81 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
82 sections.
83
Douglas Raillardd7c21b72017-06-28 15:23:03 +010084- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
85 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
86 r0p4 and onwards, this errata is enabled by default in hardware.
87
Douglas Raillardb52353a2017-07-17 14:14:52 +010088- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
89 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
90 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
91 which are 4kB aligned.
92
Douglas Raillardd7c21b72017-06-28 15:23:03 +010093- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
94 CPUs. Though the erratum is present in every revision of the CPU,
95 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleux15530dd2019-02-08 15:26:36 +010096 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010097 Earlier revisions of the CPU have other errata which require the same
98 workaround in software, so they should be covered anyway.
99
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100100For Cortex-A57, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100101
102- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
103 CPU. This needs to be enabled only for revision r0p0 of the CPU.
104
105- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
106 CPU. This needs to be enabled only for revision r0p0 of the CPU.
107
108- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
109 CPU. This needs to be enabled only for revision r0p0 of the CPU.
110
111- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
112 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
113
114- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
115 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
116
117- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
118 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
119
120- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
121 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
122
123- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
124 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
125
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100126- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
127 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
128
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100129
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100130For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100131
132- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
133 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
134
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100135DSU Errata Workarounds
136----------------------
137
138Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
139Shared Unit) errata. The DSU errata details can be found in the respective Arm
140documentation:
141
142- `Arm DSU Software Developers Errata Notice`_.
143
144Each erratum is identified by an ``ID``, as defined in the DSU errata notice
145document. Thus, the build flags which enable/disable the errata workarounds
146have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
147of DSU errata workarounds are similar to `CPU errata workarounds`_.
148
149For DSU errata, the following build flags are defined:
150
151- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
152 affected DSU configurations. This errata applies only for those DSUs that
153 contain the ACP interface **and** the DSU revision is older than r2p0 (on
154 r2p0 it is fixed). However, please note that this workaround results in
155 increased DSU power consumption on idle.
156
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100157CPU Specific optimizations
158--------------------------
159
160This section describes some of the optimizations allowed by the CPU micro
161architecture that can be enabled by the platform as desired.
162
163- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
164 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
165 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
166 of the L2 by set/way flushes any dirty lines from the L1 as well. This
167 is a known safe deviation from the Cortex-A57 TRM defined power down
168 sequence. Each Cortex-A57 based platform must make its own decision on
169 whether to use the optimization.
170
171- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
172 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
173 in a way most programmers expect, and will most probably result in a
Dan Handley610e7e12018-03-01 18:44:00 +0000174 significant speed degradation to any code that employs them. The Armv8-A
175 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100176 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
177 flag enforces this behaviour. This needs to be enabled only for revisions
178 <= r0p3 of the CPU and is enabled by default.
179
180- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
181 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
182 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
183 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
184 `Cortex-A57 Software Optimization Guide`_.
185
186--------------
187
Dan Handley610e7e12018-03-01 18:44:00 +0000188*Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100189
John Tsichritzis3eeac412018-09-04 10:56:53 +0100190.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
191.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Paul Beesley2437ddc2019-02-08 16:43:05 +0000192.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
193.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100194.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100195.. _Firmware Design guide: firmware-design.rst
196.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100197.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html