Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 1 | /* |
johpow01 | 9603f98 | 2020-05-29 14:17:38 -0500 | [diff] [blame] | 2 | * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A76_H |
| 8 | #define CORTEX_A76_H |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 12 | /* Cortex-A76 MIDR for revision 0 */ |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 13 | #define CORTEX_A76_MIDR U(0x410fd0b0) |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 19 | #define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4 |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 20 | |
Louis Mayencourt | adda9d4 | 2019-02-25 11:37:38 +0000 | [diff] [blame] | 21 | #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24) |
Soby Mathew | 1d3ba1c | 2019-05-01 09:43:18 +0100 | [diff] [blame] | 22 | #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51) |
johpow01 | 5c9ed08 | 2020-06-02 15:02:28 -0500 | [diff] [blame] | 23 | #define CORTEX_A76_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) |
Louis Mayencourt | adda9d4 | 2019-02-25 11:37:38 +0000 | [diff] [blame] | 24 | |
Dimitris Papastamos | 312e17e | 2018-05-16 09:59:54 +0100 | [diff] [blame] | 25 | /******************************************************************************* |
| 26 | * CPU Auxiliary Control register specific definitions. |
| 27 | ******************************************************************************/ |
Louis Mayencourt | 59fa218 | 2019-02-25 15:17:44 +0000 | [diff] [blame] | 28 | #define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 29 | |
| 30 | #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6) |
| 31 | |
Soby Mathew | 1d3ba1c | 2019-05-01 09:43:18 +0100 | [diff] [blame] | 32 | #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) |
| 33 | |
Dimitris Papastamos | 312e17e | 2018-05-16 09:59:54 +0100 | [diff] [blame] | 34 | #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 35 | |
johpow01 | 9603f98 | 2020-05-29 14:17:38 -0500 | [diff] [blame] | 36 | #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) |
| 37 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 38 | #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16) |
Dimitris Papastamos | 312e17e | 2018-05-16 09:59:54 +0100 | [diff] [blame] | 39 | |
Soby Mathew | 1d3ba1c | 2019-05-01 09:43:18 +0100 | [diff] [blame] | 40 | #define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2 |
| 41 | |
| 42 | #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) |
| 43 | |
| 44 | |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 45 | /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */ |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 46 | #define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1) |
Isla Mitchell | ea84d6b | 2017-08-03 16:04:46 +0100 | [diff] [blame] | 47 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 48 | #endif /* CORTEX_A76_H */ |