Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 7a4ff68 | 2017-03-28 13:56:21 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 11 | #include <arch.h> |
| 12 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <common/debug.h> |
| 14 | #include <drivers/delay_timer.h> |
Isla Mitchell | e363146 | 2017-07-14 10:46:32 +0100 | [diff] [blame] | 15 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <lib/mmio.h> |
| 17 | #include <lib/psci/psci.h> |
| 18 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 19 | #include <flowctrl.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 20 | #include <pmc.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 21 | #include <tegra_def.h> |
| 22 | #include <tegra_private.h> |
| 23 | |
| 24 | /* |
| 25 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 26 | * signals: CPU reset (3:0) and Core reset (19:16) |
| 27 | */ |
| 28 | #define CPU_CMPLX_RESET_CLR 0x344 |
| 29 | #define CPU_CORE_RESET_MASK 0x10001 |
| 30 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 31 | /* Clock and Reset controller registers for system clock's settings */ |
| 32 | #define SCLK_RATE 0x30 |
| 33 | #define SCLK_BURST_POLICY 0x28 |
| 34 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 35 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 36 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
| 37 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 38 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 39 | psci_power_state_t *req_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 40 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 41 | int state_id = psci_get_pstate_id(power_state); |
| 42 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
| 43 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 44 | /* |
| 45 | * Sanity check the requested state id, power level and CPU number. |
| 46 | * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU |
| 47 | * i.e. CPU 0 |
| 48 | */ |
Varun Wadekar | 6077dce | 2016-01-27 11:31:06 -0800 | [diff] [blame] | 49 | if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 50 | ERROR("unsupported state id @ power level\n"); |
| 51 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 52 | } |
| 53 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 54 | /* Set lower power states to PLAT_MAX_OFF_STATE */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 55 | for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 56 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 57 | |
| 58 | /* Set the SYSTEM_SUSPEND state-id */ |
| 59 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 60 | PSTATE_ID_SOC_POWERDN; |
| 61 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 62 | return PSCI_E_SUCCESS; |
| 63 | } |
| 64 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 65 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 66 | { |
| 67 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 68 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 69 | |
| 70 | if (cpu_powergate_mask[cpu] == 0) { |
| 71 | |
| 72 | /* Deassert CPU reset signals */ |
| 73 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
| 74 | |
| 75 | /* Power on CPU using PMC */ |
| 76 | tegra_pmc_cpu_on(cpu); |
| 77 | |
| 78 | /* Fill in the CPU powergate mask */ |
| 79 | cpu_powergate_mask[cpu] = 1; |
| 80 | |
| 81 | } else { |
| 82 | /* Power on CPU using Flow Controller */ |
| 83 | tegra_fc_cpu_on(cpu); |
| 84 | } |
| 85 | |
| 86 | return PSCI_E_SUCCESS; |
| 87 | } |
| 88 | |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 89 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
| 90 | { |
| 91 | /* |
| 92 | * Lock scratch registers which hold the CPU vectors |
| 93 | */ |
| 94 | tegra_pmc_lock_cpu_vectors(); |
| 95 | |
| 96 | return PSCI_E_SUCCESS; |
| 97 | } |
| 98 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 99 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 100 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 101 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | d43583c | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 102 | |
| 103 | /* Disable DCO operations */ |
| 104 | denver_disable_dco(); |
| 105 | |
| 106 | /* Power down the CPU */ |
| 107 | write_actlr_el1(DENVER_CPU_STATE_POWER_DOWN); |
| 108 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 109 | return PSCI_E_SUCCESS; |
| 110 | } |
| 111 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 112 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 113 | { |
Antonio Nino Diaz | 7a4ff68 | 2017-03-28 13:56:21 +0100 | [diff] [blame] | 114 | #if ENABLE_ASSERTIONS |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 115 | int cpu = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 116 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 117 | /* SYSTEM_SUSPEND only on CPU0 */ |
| 118 | assert(cpu == 0); |
| 119 | #endif |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 120 | |
| 121 | /* Allow restarting CPU #1 using PMC on suspend exit */ |
| 122 | cpu_powergate_mask[1] = 0; |
| 123 | |
| 124 | /* Program FC to enter suspend state */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 125 | tegra_fc_cpu_powerdn(read_mpidr()); |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 126 | |
Varun Wadekar | d43583c | 2016-02-22 11:09:41 -0800 | [diff] [blame] | 127 | /* Disable DCO operations */ |
| 128 | denver_disable_dco(); |
| 129 | |
| 130 | /* Program the suspend state ID */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 131 | write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]); |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 132 | |
| 133 | return PSCI_E_SUCCESS; |
| 134 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 135 | |
| 136 | int tegra_soc_prepare_system_reset(void) |
| 137 | { |
| 138 | /* |
| 139 | * Set System Clock (SCLK) to POR default so that the clock source |
| 140 | * for the PMC APB clock would not be changed due to system reset. |
| 141 | */ |
| 142 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
| 143 | SCLK_BURST_POLICY_DEFAULT); |
| 144 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 145 | |
| 146 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 147 | mdelay(1); |
| 148 | |
| 149 | return PSCI_E_SUCCESS; |
| 150 | } |