Tegra: remove support for legacy platform APIs
This patch modifies the Tegra port to support the new platform
APIs so that we can disable the compat layer. This includes
modifications to the power management and platform topology code.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
index 46e5940..48a2fba 100644
--- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
@@ -56,28 +56,55 @@
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
-int32_t tegra_soc_validate_power_state(unsigned int power_state)
+int32_t tegra_soc_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
{
+ int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+ int state_id = psci_get_pstate_id(power_state);
+ int cpu = read_mpidr() & MPIDR_CPU_MASK;
+
+ if (pwr_lvl > PLAT_MAX_PWR_LVL)
+ return PSCI_E_INVALID_PARAMS;
+
/* Sanity check the requested afflvl */
if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) {
/*
* It's possible to enter standby only on affinity level 0 i.e.
* a cpu on Tegra. Ignore any other affinity level.
*/
- if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0)
+ if (pwr_lvl != MPIDR_AFFLVL0)
return PSCI_E_INVALID_PARAMS;
+
+ /* power domain in standby state */
+ req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE;
+
+ return PSCI_E_SUCCESS;
}
- /* Sanity check the requested state id */
- if (psci_get_pstate_id(power_state) != PLAT_SYS_SUSPEND_STATE_ID) {
- ERROR("unsupported state id\n");
- return PSCI_E_NOT_SUPPORTED;
+ /*
+ * Sanity check the requested state id, power level and CPU number.
+ * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
+ * i.e. CPU 0
+ */
+ if ((pwr_lvl != PLAT_MAX_PWR_LVL) ||
+ (state_id != PSTATE_ID_SOC_POWERDN) ||
+ (cpu != 0)) {
+ ERROR("unsupported state id @ power level\n");
+ return PSCI_E_INVALID_PARAMS;
}
+ /* Set lower power states to PLAT_MAX_OFF_STATE */
+ for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
+ req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
+
+ /* Set the SYSTEM_SUSPEND state-id */
+ req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
+ PSTATE_ID_SOC_POWERDN;
+
return PSCI_E_SUCCESS;
}
-int tegra_soc_prepare_cpu_on(unsigned long mpidr)
+int tegra_soc_pwr_domain_on(u_register_t mpidr)
{
int cpu = mpidr & MPIDR_CPU_MASK;
uint32_t mask = CPU_CORE_RESET_MASK << cpu;
@@ -101,29 +128,29 @@
return PSCI_E_SUCCESS;
}
-int tegra_soc_prepare_cpu_off(unsigned long mpidr)
+int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
- tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK);
+ tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
return PSCI_E_SUCCESS;
}
-int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
+int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
- /* Nothing to be done for lower affinity levels */
- if (afflvl < MPIDR_AFFLVL2)
- return PSCI_E_SUCCESS;
+#if DEBUG
+ int cpu = read_mpidr() & MPIDR_CPU_MASK;
- /* Enter system suspend state */
- tegra_pm_system_suspend_entry();
+ /* SYSTEM_SUSPEND only on CPU0 */
+ assert(cpu == 0);
+#endif
/* Allow restarting CPU #1 using PMC on suspend exit */
cpu_powergate_mask[1] = 0;
/* Program FC to enter suspend state */
- tegra_fc_cpu_idle(read_mpidr());
+ tegra_fc_cpu_powerdn(read_mpidr());
/* Suspend DCO operations */
- write_actlr_el1(id);
+ write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
return PSCI_E_SUCCESS;
}