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Samuel Hollandb8566642017-08-12 04:07:39 -05001/*
Samuel Hollandfde9e1c2020-12-13 21:26:36 -06002 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
Samuel Hollandb8566642017-08-12 04:07:39 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Samuel Hollandb8566642017-08-12 04:07:39 -05009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
11#include <lib/utils_def.h>
12#include <plat/common/common_def.h>
13
Samuel Hollandb8566642017-08-12 04:07:39 -050014#include <sunxi_mmap.h>
Samuel Hollandb8566642017-08-12 04:07:39 -050015
Andre Przywaracd1c67e2020-11-28 01:38:15 +000016#ifdef SUNXI_BL31_IN_DRAM
Andre Przywara2d42e5f2020-11-28 01:39:17 +000017
18#define BL31_BASE SUNXI_DRAM_BASE
19#define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000)
20
21#define MAX_XLAT_TABLES 4
22#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
23
24#define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE
25
Andre Przywaracd1c67e2020-11-28 01:38:15 +000026#else /* !SUNXI_BL31_IN_DRAM */
27
Icenowy Zheng431b4e82021-07-23 11:35:24 +080028#define BL31_BASE (SUNXI_SRAM_A2_BASE + \
29 SUNXI_SRAM_A2_BL31_OFFSET)
Samuel Hollandd002f3b2019-12-29 12:22:55 -060030#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \
31 SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
Samuel Hollandb8566642017-08-12 04:07:39 -050032
Samuel Hollandd00eaa22019-10-27 14:07:52 -050033/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
34#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
35#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
36
Andre Przywaracd1c67e2020-11-28 01:38:15 +000037#define MAX_XLAT_TABLES 1
38#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
Andre Przywaracd1c67e2020-11-28 01:38:15 +000039
Samuel Holland0dab35d2020-12-13 20:22:42 -060040#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE
Andre Przywaracd1c67e2020-11-28 01:38:15 +000041
Samuel Hollanddf362a22021-04-04 15:54:17 -050042/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
43#define SUNXI_SCP_BASE BL31_LIMIT
44#define SUNXI_SCP_SIZE 0x4000
45
Samuel Holland0dab35d2020-12-13 20:22:42 -060046#endif /* SUNXI_BL31_IN_DRAM */
Andre Przywarab3fddff2018-09-20 21:13:55 +010047
Andre Przywaraea5fa472018-09-16 02:08:06 +010048/* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
Andre Przywarab3fddff2018-09-20 21:13:55 +010049#define SUNXI_DRAM_MAP_SIZE (64U << 20)
50
Samuel Hollandb8566642017-08-12 04:07:39 -050051#define CACHE_WRITEBACK_SHIFT 6
52#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
53
Samuel Holland0dab35d2020-12-13 20:22:42 -060054#define MAX_STATIC_MMAP_REGIONS 3
Samuel Holland3683f3e2020-12-13 20:45:49 -060055#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
Samuel Hollandb8566642017-08-12 04:07:39 -050056
Samuel Holland103ee9b2018-10-21 12:41:03 -050057#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
58 (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
59
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010060#define PLAT_MAX_PWR_LVL_STATES U(2)
61#define PLAT_MAX_RET_STATE U(1)
62#define PLAT_MAX_OFF_STATE U(2)
Samuel Hollandb8566642017-08-12 04:07:39 -050063
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010064#define PLAT_MAX_PWR_LVL U(2)
Deepika Bhavnanifa4e1d02019-12-13 10:48:27 -060065#define PLAT_NUM_PWR_DOMAINS (U(1) + \
Samuel Hollandb8566642017-08-12 04:07:39 -050066 PLATFORM_CLUSTER_COUNT + \
67 PLATFORM_CORE_COUNT)
68
69#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
Samuel Hollandb8566642017-08-12 04:07:39 -050070
Deepika Bhavnanifa4e1d02019-12-13 10:48:27 -060071#define PLATFORM_CLUSTER_COUNT U(1)
Samuel Hollandb8566642017-08-12 04:07:39 -050072#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
73 PLATFORM_MAX_CPUS_PER_CLUSTER)
Deepika Bhavnanifa4e1d02019-12-13 10:48:27 -060074#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
Samuel Hollandb8566642017-08-12 04:07:39 -050075#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
76
Amit Singh Tomar2f372242018-06-20 00:44:50 +053077#ifndef SPD_none
78#ifndef BL32_BASE
79#define BL32_BASE SUNXI_DRAM_BASE
80#endif
81#endif
82
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010083#endif /* PLATFORM_DEF_H */