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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Samarth Parikh59cfa132017-11-23 14:23:21 +05302 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Sandrine Bailleux04b66d82015-03-18 14:52:53 +00007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <platform_def.h>
10
11#include <arch_helpers.h>
12#include <lib/bakery_lock.h>
13#include <lib/mmio.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000014#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015
Dan Handley9df48042015-03-19 18:58:55 +000016#include "css_mhu.h"
17
18/* SCP MHU secure channel registers */
19#define SCP_INTR_S_STAT 0x200
20#define SCP_INTR_S_SET 0x208
21#define SCP_INTR_S_CLEAR 0x210
22
23/* CPU MHU secure channel registers */
24#define CPU_INTR_S_STAT 0x300
25#define CPU_INTR_S_SET 0x308
26#define CPU_INTR_S_CLEAR 0x310
27
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +010028ARM_INSTANTIATE_LOCK;
Dan Handley9df48042015-03-19 18:58:55 +000029
30/* Weak definition may be overridden in specific CSS based platform */
31#pragma weak plat_arm_pwrc_setup
32
33
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000034/*
35 * Slot 31 is reserved because the MHU hardware uses this register bit to
36 * indicate a non-secure access attempt. The total number of available slots is
37 * therefore 31 [30:0].
38 */
39#define MHU_MAX_SLOT_ID 30
40
41void mhu_secure_message_start(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000042{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000043 assert(slot_id <= MHU_MAX_SLOT_ID);
44
Dan Handley9df48042015-03-19 18:58:55 +000045 arm_lock_get();
46
47 /* Make sure any previous command has finished */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000048 while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
49 (1 << slot_id))
Dan Handley9df48042015-03-19 18:58:55 +000050 ;
51}
52
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000053void mhu_secure_message_send(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000054{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000055 assert(slot_id <= MHU_MAX_SLOT_ID);
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000056 assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) &
57 (1 << slot_id)));
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000058
59 /* Send command to SCP */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000060 mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +000061}
62
63uint32_t mhu_secure_message_wait(void)
64{
65 /* Wait for response from SCP */
66 uint32_t response;
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000067 while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT)))
Dan Handley9df48042015-03-19 18:58:55 +000068 ;
69
70 return response;
71}
72
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000073void mhu_secure_message_end(unsigned int slot_id)
Dan Handley9df48042015-03-19 18:58:55 +000074{
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000075 assert(slot_id <= MHU_MAX_SLOT_ID);
76
Dan Handley9df48042015-03-19 18:58:55 +000077 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000078 * Clear any response we got by writing one in the relevant slot bit to
79 * the CLEAR register
Dan Handley9df48042015-03-19 18:58:55 +000080 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000081 mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id);
Dan Handley9df48042015-03-19 18:58:55 +000082
83 arm_lock_release();
84}
85
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +010086void __init mhu_secure_init(void)
Dan Handley9df48042015-03-19 18:58:55 +000087{
88 arm_lock_init();
89
90 /*
Sandrine Bailleux04b66d82015-03-18 14:52:53 +000091 * The STAT register resets to zero. Ensure it is in the expected state,
92 * as a stale or garbage value would make us think it's a message we've
93 * already sent.
Dan Handley9df48042015-03-19 18:58:55 +000094 */
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +000095 assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0);
Dan Handley9df48042015-03-19 18:58:55 +000096}
97
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +010098void __init plat_arm_pwrc_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +000099{
100 mhu_secure_init();
101}