blob: 3e2d79daafd90e4c1c2d2aabf92d381cb0f75d39 [file] [log] [blame]
Haojian Zhuang602362d2017-06-01 12:15:14 +08001/*
Haojian Zhuang1b4b4122018-01-25 16:13:05 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang602362d2017-06-01 12:15:14 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Haojian Zhuang602362d2017-06-01 12:15:14 +08009
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
12
Haojian Zhuang602362d2017-06-01 12:15:14 +080013#include "../hikey960_def.h"
14
Victor Chong2d9a42d2017-08-17 15:21:10 +090015/* Special value used to verify platform parameters from BL2 to BL3-1 */
16#define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
Haojian Zhuang602362d2017-06-01 12:15:14 +080017
18/*
19 * Generic platform constants
20 */
21
22/* Size of cacheable stacks */
Teddy Reeddd3f0a82018-09-03 17:38:50 -040023#define PLATFORM_STACK_SIZE 0x1000
Haojian Zhuang602362d2017-06-01 12:15:14 +080024
25#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
26
27#define PLATFORM_CACHE_LINE_SIZE 64
28#define PLATFORM_CLUSTER_COUNT 2
29#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
30#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
31 PLATFORM_CORE_COUNT_PER_CLUSTER)
32#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
33#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
34 PLATFORM_CLUSTER_COUNT + 1)
35
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010036#define PLAT_MAX_RET_STATE U(1)
37#define PLAT_MAX_OFF_STATE U(2)
Haojian Zhuang602362d2017-06-01 12:15:14 +080038
39#define MAX_IO_DEVICES 3
40#define MAX_IO_HANDLES 4
41/* UFS RPMB and UFS User Data */
Yann Gautier37966212018-12-03 13:38:06 +010042#define MAX_IO_BLOCK_DEVICES U(2)
Haojian Zhuang602362d2017-06-01 12:15:14 +080043
44
45/*
46 * Platform memory map related constants
47 */
48
49/*
50 * BL1 specific defines.
51 */
52#define BL1_RO_BASE (0x1AC00000)
Teddy Reeddd3f0a82018-09-03 17:38:50 -040053#define BL1_RO_LIMIT (BL1_RO_BASE + 0x20000)
54#define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */
Haojian Zhuang602362d2017-06-01 12:15:14 +080055#define BL1_RW_SIZE (0x00188000)
56#define BL1_RW_LIMIT (0x1B000000)
57
58/*
59 * BL2 specific defines.
60 */
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080061#define BL2_BASE (0x1AC00000)
62#define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
Haojian Zhuang602362d2017-06-01 12:15:14 +080063
64/*
65 * BL31 specific defines.
66 */
67#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
68#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
69
Victor Chong91287682017-05-28 00:14:37 +090070/*
71 * BL3-2 specific defines.
72 */
73
74/*
75 * The TSP currently executes from TZC secured area of DRAM.
76 */
77#define BL32_DRAM_BASE DDR_SEC_BASE
78#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
79
Victor Chong7d787f52017-08-16 13:53:56 +090080#ifdef SPD_opteed
81/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
82#define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
83#define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
84#endif
Victor Chong7d787f52017-08-16 13:53:56 +090085
Victor Chong91287682017-05-28 00:14:37 +090086#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
87#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
88#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
89#define BL32_BASE BL32_DRAM_BASE
90#define BL32_LIMIT BL32_DRAM_LIMIT
91#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
92#error "SRAM storage of TSP payload is currently unsupported"
93#else
94#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
95#endif
96
Victor Chong398d5d32017-09-14 01:27:19 +090097/* BL32 is mandatory in AArch32 */
98#ifndef AARCH32
99#ifdef SPD_none
100#undef BL32_BASE
101#endif /* SPD_none */
102#endif
103
Haojian Zhuang602362d2017-06-01 12:15:14 +0800104#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
105#define NS_BL1U_SIZE (0x00100000)
106#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
107
Teddy Reeddd3f0a82018-09-03 17:38:50 -0400108#define HIKEY960_NS_IMAGE_OFFSET (0x1AC28000) /* offset in l-loader */
Haojian Zhuang602362d2017-06-01 12:15:14 +0800109#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
110
Victor Chong2d9a42d2017-08-17 15:21:10 +0900111#define SCP_BL2_BASE (0x89C80000)
112#define SCP_BL2_SIZE (0x00040000)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800113
114/*
115 * Platform specific page table and MMU setup constants
116 */
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +0100117#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
118#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800119
Roberto Vargas82477962017-10-23 08:22:17 +0100120#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800121#define MAX_XLAT_TABLES 3
122#endif
123
Roberto Vargas82477962017-10-23 08:22:17 +0100124#ifdef IMAGE_BL2
Victor Chong7d787f52017-08-16 13:53:56 +0900125#ifdef SPD_opteed
126#define MAX_XLAT_TABLES 4
127#else
128#define MAX_XLAT_TABLES 3
129#endif
Victor Chong7d787f52017-08-16 13:53:56 +0900130#endif
131
Haojian Zhuang602362d2017-06-01 12:15:14 +0800132#define MAX_MMAP_REGIONS 16
133
134/*
135 * Declarations and constants to access the mailboxes safely. Each mailbox is
136 * aligned on the biggest cache line size in the platform. This is known only
137 * to the platform as it might have a combination of integrated and external
138 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
139 * line at any cache level. They could belong to different cpus/clusters &
140 * get written while being protected by different locks causing corruption of
141 * a valid mailbox address.
142 */
143#define CACHE_WRITEBACK_SHIFT 6
144#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
145
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100146#endif /* PLATFORM_DEF_H */