hikey960: Add BL32 (OP-TEE) support
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 369117b..8bf32c3 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -63,6 +63,27 @@
#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
+/*
+ * BL3-2 specific defines.
+ */
+
+/*
+ * The TSP currently executes from TZC secured area of DRAM.
+ */
+#define BL32_DRAM_BASE DDR_SEC_BASE
+#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
+
+#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
+#define BL32_BASE BL32_DRAM_BASE
+#define BL32_LIMIT BL32_DRAM_LIMIT
+#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
+#error "SRAM storage of TSP payload is currently unsupported"
+#else
+#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
+#endif
+
#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
#define NS_BL1U_SIZE (0x00100000)
#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
@@ -70,7 +91,7 @@
#define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */
#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
-#define SCP_BL2_BASE BL31_BASE
+#define SCP_BL2_BASE BL31_BASE /* 1AC5_8000 */
#define SCP_MEM_BASE (0x89C80000)
#define SCP_MEM_SIZE (0x00040000)
@@ -80,7 +101,7 @@
*/
#define ADDR_SPACE_SIZE (1ull << 32)
-#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31
+#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 || IMAGE_BL32
#define MAX_XLAT_TABLES 3
#endif