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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dimitris Papastamos04159512018-01-22 11:53:04 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +01008#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +01009#include <context.h>
dp-arm3cac7862016-09-19 11:18:44 +010010#include <cpu_data.h>
Achin Gupta9cf2bb72014-05-09 11:07:09 +010011#include <interrupt_mgmt.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010012#include <platform_def.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010013#include <runtime_svc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
15 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010016
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000017 .globl sync_exception_sp_el0
18 .globl irq_sp_el0
19 .globl fiq_sp_el0
20 .globl serror_sp_el0
21
22 .globl sync_exception_sp_elx
23 .globl irq_sp_elx
24 .globl fiq_sp_elx
25 .globl serror_sp_elx
26
27 .globl sync_exception_aarch64
28 .globl irq_aarch64
29 .globl fiq_aarch64
30 .globl serror_aarch64
31
32 .globl sync_exception_aarch32
33 .globl irq_aarch32
34 .globl fiq_aarch32
35 .globl serror_aarch32
36
Douglas Raillard0980eed2016-11-09 17:48:27 +000037 /* ---------------------------------------------------------------------
38 * This macro handles Synchronous exceptions.
39 * Only SMC exceptions are supported.
40 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +010041 */
42 .macro handle_sync_exception
Achin Guptaed1744e2014-08-04 23:13:10 +010043 /* Enable the SError interrupt */
44 msr daifclr, #DAIF_ABT_BIT
45
Achin Gupta9cf2bb72014-05-09 11:07:09 +010046 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
dp-arm3cac7862016-09-19 11:18:44 +010047
48#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +010049 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +000050 * Read the timestamp value and store it in per-cpu data. The value
51 * will be extracted from per-cpu data by the C level SMC handler and
52 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +010053 */
54 mrs x30, cntpct_el0
55 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
56 mrs x29, tpidr_el3
57 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
58 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
59#endif
60
Achin Gupta9cf2bb72014-05-09 11:07:09 +010061 mrs x30, esr_el3
62 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
63
Douglas Raillard0980eed2016-11-09 17:48:27 +000064 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +010065 cmp x30, #EC_AARCH32_SMC
66 b.eq smc_handler32
67
68 cmp x30, #EC_AARCH64_SMC
69 b.eq smc_handler64
70
Douglas Raillard0980eed2016-11-09 17:48:27 +000071 /* Other kinds of synchronous exceptions are not handled */
Julius Werner67ebde72017-07-27 14:59:34 -070072 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
73 b report_unhandled_exception
Achin Gupta9cf2bb72014-05-09 11:07:09 +010074 .endm
75
76
Douglas Raillard0980eed2016-11-09 17:48:27 +000077 /* ---------------------------------------------------------------------
78 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
79 * interrupts.
80 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +010081 */
82 .macro handle_interrupt_exception label
Achin Guptaed1744e2014-08-04 23:13:10 +010083 /* Enable the SError interrupt */
84 msr daifclr, #DAIF_ABT_BIT
85
Achin Gupta9cf2bb72014-05-09 11:07:09 +010086 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
87 bl save_gp_registers
88
Douglas Raillard0980eed2016-11-09 17:48:27 +000089 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +010090 mrs x0, spsr_el3
91 mrs x1, elr_el3
92 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
93
Achin Gupta9cf2bb72014-05-09 11:07:09 +010094 /* Switch to the runtime stack i.e. SP_EL0 */
95 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
96 mov x20, sp
97 msr spsel, #0
98 mov sp, x2
99
100 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000101 * Find out whether this is a valid interrupt type.
102 * If the interrupt controller reports a spurious interrupt then return
103 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100104 */
Dan Handley701fea72014-05-27 16:17:21 +0100105 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100106 cmp x0, #INTR_TYPE_INVAL
107 b.eq interrupt_exit_\label
108
109 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000110 * Get the registered handler for this interrupt type.
111 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100112 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000113 * a. An interrupt of a type was routed correctly but a handler for its
114 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100115 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000116 * b. An interrupt of a type was not routed correctly so a handler for
117 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100118 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000119 * c. An interrupt of a type was routed correctly to EL3, but was
120 * deasserted before its pending state could be read. Another
121 * interrupt of a different type pended at the same time and its
122 * type was reported as pending instead. However, a handler for this
123 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100124 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000125 * a. and b. can only happen due to a programming error. The
126 * occurrence of c. could be beyond the control of Trusted Firmware.
127 * It makes sense to return from this exception instead of reporting an
128 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100129 */
130 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100131 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100132 mov x21, x0
133
134 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100135
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100136 /* Set the current security state in the 'flags' parameter */
137 mrs x2, scr_el3
138 ubfx x1, x2, #0, #1
139
140 /* Restore the reference to the 'handle' i.e. SP_EL3 */
141 mov x2, x20
142
Douglas Raillard0980eed2016-11-09 17:48:27 +0000143 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100144 mov x3, xzr
145
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100146 /* Call the interrupt type handler */
147 blr x21
148
149interrupt_exit_\label:
150 /* Return from exception, possibly in a different security state */
151 b el3_exit
152
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100153 .endm
154
155
Dimitris Papastamos04159512018-01-22 11:53:04 +0000156 .macro save_x4_to_x29_sp_el0
157 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
158 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
159 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
160 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
161 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
162 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
163 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100164 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
165 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
166 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
167 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
168 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
169 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
170 mrs x18, sp_el0
171 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
172 .endm
173
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100174
175vector_base runtime_exceptions
176
Douglas Raillard0980eed2016-11-09 17:48:27 +0000177 /* ---------------------------------------------------------------------
178 * Current EL with SP_EL0 : 0x0 - 0x200
179 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100180 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100181vector_entry sync_exception_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000182 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700183 b report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000184 check_vector_size sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100185
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100186vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000187 /*
188 * EL3 code is non-reentrant. Any asynchronous exception is a serious
189 * error. Loop infinitely.
190 */
Julius Werner67ebde72017-07-27 14:59:34 -0700191 b report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000192 check_vector_size irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100194
195vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700196 b report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000197 check_vector_size fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100199
200vector_entry serror_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700201 b report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000202 check_vector_size serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203
Douglas Raillard0980eed2016-11-09 17:48:27 +0000204 /* ---------------------------------------------------------------------
205 * Current EL with SP_ELx: 0x200 - 0x400
206 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100208vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000209 /*
210 * This exception will trigger if anything went wrong during a previous
211 * exception entry or exit or while handling an earlier unexpected
212 * synchronous exception. There is a high probability that SP_EL3 is
213 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000214 */
Julius Werner67ebde72017-07-27 14:59:34 -0700215 b report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000216 check_vector_size sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100218vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700219 b report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000220 check_vector_size irq_sp_elx
221
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100222vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700223 b report_unhandled_interrupt
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000224 check_vector_size fiq_sp_elx
225
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100226vector_entry serror_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700227 b report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000228 check_vector_size serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229
Douglas Raillard0980eed2016-11-09 17:48:27 +0000230 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100231 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000232 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100234vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000235 /*
236 * This exception vector will be the entry point for SMCs and traps
237 * that are unhandled at lower ELs most commonly. SP_EL3 should point
238 * to a valid cpu context where the general purpose and system register
239 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000240 */
241 handle_sync_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000242 check_vector_size sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100244vector_entry irq_aarch64
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100245 handle_interrupt_exception irq_aarch64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000246 check_vector_size irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100248vector_entry fiq_aarch64
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100249 handle_interrupt_exception fiq_aarch64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000250 check_vector_size fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100252vector_entry serror_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000253 /*
254 * SError exceptions from lower ELs are not currently supported.
255 * Report their occurrence.
256 */
Julius Werner67ebde72017-07-27 14:59:34 -0700257 b report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000258 check_vector_size serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259
Douglas Raillard0980eed2016-11-09 17:48:27 +0000260 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100261 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000262 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100263 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100264vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000265 /*
266 * This exception vector will be the entry point for SMCs and traps
267 * that are unhandled at lower ELs most commonly. SP_EL3 should point
268 * to a valid cpu context where the general purpose and system register
269 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000270 */
271 handle_sync_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000272 check_vector_size sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100273
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100274vector_entry irq_aarch32
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100275 handle_interrupt_exception irq_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000276 check_vector_size irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100278vector_entry fiq_aarch32
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100279 handle_interrupt_exception fiq_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000280 check_vector_size fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100281
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100282vector_entry serror_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000283 /*
284 * SError exceptions from lower ELs are not currently supported.
285 * Report their occurrence.
286 */
Julius Werner67ebde72017-07-27 14:59:34 -0700287 b report_unhandled_exception
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000288 check_vector_size serror_aarch32
289
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000290
Douglas Raillard0980eed2016-11-09 17:48:27 +0000291 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000292 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000293 * Depending upon the execution state from where the SMC has been
294 * invoked, it frees some general purpose registers to perform the
295 * remaining tasks. They involve finding the runtime service handler
296 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
297 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000298 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000299 * Note that x30 has been explicitly saved and can be used here
300 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000301 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000302func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000303smc_handler32:
304 /* Check whether aarch32 issued an SMC64 */
305 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
306
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000307smc_handler64:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000308 /*
309 * Populate the parameters for the SMC handler.
310 * We already have x0-x4 in place. x5 will point to a cookie (not used
311 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000312 * contain flags we need to pass to the handler.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000313 *
Dimitris Papastamos04159512018-01-22 11:53:04 +0000314 * Save x4-x29 and sp_el0. Refer to SMCCC v1.1.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000315 */
Dimitris Papastamos04159512018-01-22 11:53:04 +0000316 save_x4_to_x29_sp_el0
Soby Mathew6c5192a2014-04-30 15:36:37 +0100317
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000318 mov x5, xzr
319 mov x6, sp
320
321 /* Get the unique owning entity number */
322 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
323 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
324 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
325
326 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
327
328 /* Load descriptor index from array of indices */
329 adr x14, rt_svc_descs_indices
330 ldrb w15, [x14, x16]
331
Douglas Raillard0980eed2016-11-09 17:48:27 +0000332 /*
333 * Restore the saved C runtime stack value which will become the new
334 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
335 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000336 */
337 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
338
339 /*
340 * Any index greater than 127 is invalid. Check bit 7 for
341 * a valid index
342 */
343 tbnz w15, 7, smc_unknown
344
345 /* Switch to SP_EL0 */
346 msr spsel, #0
347
Douglas Raillard0980eed2016-11-09 17:48:27 +0000348 /*
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000349 * Get the descriptor using the index
350 * x11 = (base + off), x15 = index
351 *
352 * handler = (base + off) + (index << log2(size))
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000353 */
354 lsl w10, w15, #RT_SVC_SIZE_LOG2
355 ldr x15, [x11, w10, uxtw]
356
Douglas Raillard0980eed2016-11-09 17:48:27 +0000357 /*
358 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
359 * switch during SMC handling.
360 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000361 */
362 mrs x16, spsr_el3
363 mrs x17, elr_el3
364 mrs x18, scr_el3
365 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100366 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000367
368 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
369 bfi x7, x18, #0, #1
370
371 mov sp, x12
372
Douglas Raillard0980eed2016-11-09 17:48:27 +0000373 /*
374 * Call the Secure Monitor Call handler and then drop directly into
375 * el3_exit() which will program any remaining architectural state
376 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000377 */
378#if DEBUG
379 cbz x15, rt_svc_fw_critical_error
380#endif
381 blr x15
382
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100383 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100384
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000385smc_unknown:
386 /*
387 * Here we restore x4-x18 regardless of where we came from. AArch32
388 * callers will find the registers contents unchanged, but AArch64
389 * callers will find the registers modified (with stale earlier NS
390 * content). Either way, we aren't leaking any secure information
Douglas Raillard0980eed2016-11-09 17:48:27 +0000391 * through them.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000392 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000393 mov x0, #SMC_UNK
Soby Mathew5e5c2072014-04-07 15:28:55 +0100394 b restore_gp_registers_callee_eret
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000395
396smc_prohibited:
Soby Mathew6c5192a2014-04-30 15:36:37 +0100397 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000398 mov x0, #SMC_UNK
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000399 eret
400
401rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000402 /* Switch to SP_ELx */
403 msr spsel, #1
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000404 no_ret report_unhandled_exception
Kévin Petita877c252015-03-24 14:03:57 +0000405endfunc smc_handler